Broadcom Reference Design
Clock Generator
CY26187-1
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07130 Rev. *A
Revised December 14, 2002
2CY26187-1-1CY2295
Features
Benefits
Integrated phase-locked loop
Highest performance PLL tailored for multimedia applications
Low skew, low jitter, high accuracy outputs
Meets critical timing requirements in complex system designs
3.3V Operation
Enables system and application compatibility
Part Number
Outputs
Broadcom Reference
Design
Input Frequency
Output Frequencies
CY26187-1
2
SDK5680
25 MHz
1 copy of 142 MHz, 1 copy 35.5 MHz (3.3V)
Logic Block Diagram - CY26187-1
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
Q
P
VCO
VDD
VSS
CLK_OUT_2
OE
CLK_OUT_1
8-pin SOIC
CY26187-1
Pin Configuration
1
2
3
4
XOUT
XIN
AVSS
CLK_OUT_2
VDD
5
6
7
8
AVDD
OE
CLK_OUT_1
CY26187-1
PRELIMINARY
Document #: 38-07130 Rev. *A
Page 2 of 6
Absolute Maximum Conditions
Pin Summary CY26187-1
Name
Pin Number
Description
XIN
1
25-MHz Reference Crystal Input
AVDD
2
Analog Voltage Supply
OE
3
Output Enable (0 = off; 1 = on)
AVSS
4
Ground
VDD
5
Voltage Supply
CLK_OUT_2
6
35.5-MHz Clock Out
CLK_OUT_1
7
142-MHz Clock Out
XOUT
[1]
8
Reference Crystal Output
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
7.0
V
T
S
Storage Temperature
[2]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs referred to VDD
V
SS
0.3
V
DD
+ 0.3
V
Electro-Static Discharge
2000
V
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.135
3.3
3.465
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
15
pF
f
REF
CY26187-1 Reference Frequency
25
MHz
t
PU
Power-up time for all VDD's to reach minimum
specified voltage (power ramps must be monotonic)
0.05
500
ms
DC Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
V
OH
= V
DD
0.5, V
DD
= 3.3V
12
24
mA
I
OL
Output Low Current
V
OL
= 0.5, V
DD
= 3.3V
12
24
mA
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
I
DD
Supply Current
Sum of core and output current
35
mA
AC Electrical
Characteristics
(V
DD
= 3.3V)
[3]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V
DD
45
50
55
%
t3
Rising Edge Slew Rate
Output Clock Rise Time, 20% - 80% of V
DD
0.8
1.4
V/ns
t4
Falling Edge Slew Rate
Output Clock Fall Time, 80% - 20% of V
DD
0.8
1.4
V/ns
t9
Clock Jitter
Peak-to-Peak period jitter
300
ps
t10
PLL Lock Time
3
ms
CY26187-1
PRELIMINARY
Document #: 38-07130 Rev. *A
Page 3 of 6
Notes:
1.
Float XOUT pin if XIN is driven by reference clock (as opposed to crystal).
2.
Rated for 10 years.
3.
Not 100% tested
CY26187-1
PRELIMINARY
Document #: 38-07130 Rev. *A
Page 4 of 6
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
.
Test Circuit
0.1
F
0.1
F
V
DD
CLK out
C
LOAD
GND
OUTPUTS
AV
DD
t1
t2
CLK
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
Broadcom Reference
Design
CY26187SC-1
S8
8-Pin SOIC
Commercial
3.3V
SDK5680
CY26187-1
PRELIMINARY
Document #: 38-07130 Rev. *A
Page 5 of 6
Package Diagram
8-Lead (150-Mil) SOIC S8
51-85066-A
CY26187-1
PRELIMINARY
Document #: 38-07130 Rev. *A
Page 6 of 6
Document Title: CY26187-1 Broadcom Reference Design Clock Generator
Document Number: 38-07130
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110095
02/19/02
CKN
New data sheet
*A
121871
12/14/02
RBI
Power up requirements added to Operating Conditions Information
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