Frequency Generator for Intel

Integrated Chipset

CY28301

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07011 Rev. *C

Revised September 24, 2002

Features

· Single chip FTG solution for Intel

Solano/810E/810

· Support SMBus byte Read/Write and block Read/Write

operations to simplify system BIOS development

· Vendor ID and revision ID support
· Maximized EMI suppression using Cypress's Spread

Spectrum technology

· Low jitter and tightly controlled clock skew
· Two copies of CPU clock
· Thirteen copies of SDRAM clock
· Eight copies of PCI clock
· One copy of synchronous APIC clock
· Three copies of 66-MHz outputs
· Two copies of 48-MHz outputs
· One copy of 14.31818-MHz reference clock

Key Specifications

CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps

APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps

CPU, 3V66 Output Skew: ............................................ 175 ps

SDRAM, APIC, 48-MHz Output Skew: ........................ 250 ps

PCI Output Skew: ........................................................ 500 ps

CPU to SDRAM Skew (@ 133 MHz) ......................... ±0.5 ns

CPU to SDRAM Skew (@ 100 MHz).................. 4.5 to 5.5 ns

CPU to 3V66 Skew (@ 66 MHz) ........................ 7.0 to 8.0 ns

3V66 to PCI Skew (3V66 lead)........................... 1.5 to 3.5 ns

PCI to APIC Skew ...................................................... ±0.5 ns

VDD_REF

VDD_CPU

PCI1

XTAL

PLL REF FREQ

PLL 1

REF/FS1

PCI3:7

48MHz/FS0

24_48MHz

PLL2

OSC

VDD_48MHz

SMBus

SDATA

Logic

SCLK

3V66_0:2

CPU0:1

APIC

Divider,

Delay, and

Phase

Control

Logic

VDD_3V66

SDRAM0:11,

PCI0

PCI2/SEL24_48MHz#*

(FS0:4)

VDD_REF

X1
X2

GND_REF

GND_3V66

3V66_0
3V66_1
3V66_2

VDD_3V66

VDD_PCI

PCI0
PCI1

PCI2/SEL24_48MHz#*

GND_PCI

PCI3
PCI4
PCI5

VDD_PCI

PCI6
PCI7

GND_PCI

PD#*

SCLK

SDATA

283

REF/FS1*
VDD_APIC
APIC
VDD_CPU
CPU0
CPU1
GND_CPU
GND_SDRAM
SDRAM0
SDRAM1
SDRAM2
VDD_SDRAM
SDRAM3
SDRAM4
SDRAM5
GND_SDRAM
SDRAM6
SDRAM7
SDRAM_F
VDD_SDRAM
GND_48MHz
24_48MHz
48MHz/FS0*
VDD_48MHz

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26
27
28

31
30
29

VDD_SDRAM

SDRAM11
SDRAM10

GND_SDRAM

VDD_SDRAM
SDRAM8
SDRAM9

GND_SDRAM

VDD_APIC

SDRAM_F

VDD_SDRAM

VDD_PCI

PD#

Note:

Internal 100K pull-up resistors present on inputs marked with *. Design
should not rely solely on internal pull-up resistor to set I/O pins HIGH.

Pin Configuration

[1]

Block Diagram

CY28301

Document #: 38-07011 Rev. *C

Page 2 of 15

Pin Definitions

Pin Name

Pin No.

Pin

Type

Pin Description

REF/FS1

I/O

Reference Clock /Frequency Select 1: 3.3V 14.318-MHz clock output.
This pin also serves as the select strap to determine the device operating
frequency (as described in Table 5).

Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency
input.

Crystal Output: An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left
unconnected.

PCI0

PCI Clock 0: 3.3V 33-MHz PCI clock output.

PCI1

PCI Clock 1: 3.3V 33-MHz PCI clock output.

PCI2/SEL24_48MHz#

PCI Clock 2/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This
pin also serves as the select strap to determine the output frequency for
24_48MHz output. Logic 1 = 24 MHz on pin 35.

PCI3:7

15, 16, 17, 19,

PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be
individually turned off via the SMBus interface.

3V66_0:2

6, 7, 8

66-MHz Clock Output: 3.3V output clocks. The operating frequency is
controlled by FS0:1 (see Table 5).

48MHz/FS0

I/O

48-MHz Output/Frequency Selection 1: 3.3V 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the
device operating frequency (as described in Table 5.)

24_48MHz

24- or 48-MHz Output: 3.3V 24- or 48-MHz non-spread spectrum output.

PD#

Power-down Input: LVTTL-compatible asynchronous input that places
the device in power-down mode when held LOW.

CPU0:1

52, 51

CPU Clock Outputs: Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:1. Voltage swing is set
by VDDQ2.

SDRAM0:11,
SDRAM_F

48, 47, 46, 44,
43, 42, 40, 39,
31, 30, 27, 26,

SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The
operating frequency is controlled by FS0:1 (see Table 5).

APIC

Synchronous APIC Clock Outputs: Clock outputs running synchronous
with the PCI clock outputs. Voltage swing set by VDDQ2.

SDATA

I/O

Data pin for SMBus circuitry.

SCLK

Clock pin for SMBus circuitry.

VDD_REF,
VDD_3V66, VDD_PCI,
VDD_SDRAM,
VDD_48MHz

1, 9, 10, 18, 25,

32, 37, 45, 33

3.3V Power Connection: Power supply for SDRAM output buffers, PCI
output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.

VDD_CPU,
VDD_APIC

53, 55

2.5V Power Connection: Power supply for APIC and CPU output buffers.
Connect to 2.5V.

GND_REF,
GND_3V66,
GND_PCI,
GND_SDRAM,
GND_48MHZ,
GND_CPU

4, 5, 14, 21, 28,

29, 41, 49, 50,

Ground Connections: Connect all ground pins to the common system
ground plane.

CY28301

Document #: 38-07011 Rev. *C

Page 3 of 15

Serial Data Interface

The CY28301 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.

Data Protocol

The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write, and block Read operations from

the controller. For block Write/Read operation, the bytes must
be accessed in sequential order from lowest to highest byte
with the ability to stop after any complete byte has been trans-
ferred. For byte/word Write and byte Read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code.

The definition for the command code is defined as follows.

Table 1. Command Code Definition

Bit

Descriptions

0 = Block Read or block Write operation
1 = Byte/Word Read or byte/word Write operation

6:0

Byte offset for byte/word Read or Write operation. For block Read or Write operations, these
bits need to be set at `0000000.'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command code 8-bits
`00000000' stands for block operation

11:18

Command code 8 bits
`00000000' stands for block operation

Acknowledge from slave

20:27

Byte count 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte 0 8 bits

Read

Acknowledge from slave

38:45

Data byte 1 8 bits

30:37

Byte count from slave 8 bits

Acknowledge from slave

Acknowledge

...

Data byte N/Slave acknowledge...

39:46

Data byte from slave 8 bits

...

Data byte N 8 bits

Acknowledge

...

Acknowledge from slave

48:55

Data byte from slave 8 bits

...

Stop

Acknowledge

...

Data bytes from slave/acknowledge

...

Data byte N from slave 8 bits

...

Not acknowledge

...

Stop

CY28301

Document #: 38-07011 Rev. *C

Page 4 of 15

Table 3. Word Read and Word Write Protocol

Word Write Protocol

Word Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command Code 8-bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed

11:18

Command code 8 bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed

Acknowledge from slave

20:27

Data byte low 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

29:36

Data byte high 8 bits

Read

Acknowledge from slave

Stop

30:37

Data byte low from slave 8 bits

Acknowledge

39:46

Data byte high from slave 8 bits

Not acknowledge

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address 7 bits

2:8

Slave address 7 bits

Write

Acknowledge from slave

11:18

Command code 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed

11:18

Command code 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed

Acknowledge from slave

20:27

Data byte 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address 7 bits

Stop

Read

Acknowledge from slave

30:37

Data byte from slave 8 bits

Not Acknowledge

Stop

CY28301

Document #: 38-07011 Rev. *C

Page 5 of 15

CY28301 Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

Byte 0 Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N Bits 7, 6, 5, 4, 3, 2, 1, 0

2. All unused register bits (reserved and N/A) should be

written to a "0" level.

3. All register bits labeled "Initialize to 0" must be written to "0"

during initialization.

Byte 0: Control Register 0

Bit

Pin#

Name

Default

Description

Bit 7

SEL1

See 5

Bit 6

SEL0

See 5

Bit 5

Reserved

Bit 4

Reserved

Bit 3

FS_Override

0 = Select operating frequency by FS[1:0] input pins
1 = Select operating frequency by SEL[1:0] settings

Bit 2

Spread Select2

`000' = Normal (spread off)

`001' = Test mode

`010' = Reserved

`011' = Three-stated

`100' = 0.5%

`101' = 0.75%

`110' = 1.0%

`111' = 0.3%

Bit 1

Spread Select1

Bit 0

Spread Select0

Byte 1: Control Register 1

Bit

Pin#

Name

Default

Description

Bit 7

Latched FS1 input

Latched FS[1:0] inputs. These bits are Read-only.

Bit 6

Latched FS0 input

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

REF

(Active/Inactive)

Bit 0

REF_DRV

REF Clock output drive strength
0 = Normal
1= High drive

CY28301

Document #: 38-07011 Rev. *C

Page 6 of 15

Byte 2: Control Register 2

Bit

Pin#

Name

Default

Description

Bit 7

PCI7

(Active/Inactive)

Bit 6

PCI6

(Active/Inactive)

Bit 5

PCI5

(Active/Inactive)

Bit 4

PCI4

(Active/Inactive)

Bit 3

PCI3

(Active/Inactive)

Bit 2

PCI2

(Active/Inactive)

Bit 1

PCI1

(Active/Inactive)

Bit 0

PCI0

(Active/Inactive)

Byte 3: Control Register 3

Bit

Pin#

Name

Default

Description

Bit 7

3V66_2

(Active/Inactive)

Bit 6

3V66_1

(Active/Inactive)

Bit 5

3V66_0

(Active/Inactive)

Bit 4

APIC

(Active/Inactive)

Bit 3

Reserved

Bit 2

Reserved

Bit 1

CPU1

(Active/Inactive)

Bit 0

CPU0

(Active/Inactive)

Byte 4: Control Register 4

Bit

Pin#

Name

Default

Description

Bit 7

SDRAM7

(Active/Inactive)

Bit 6

SDRAM6

(Active/Inactive)

Bit 5

SDRAM5

(Active/Inactive)

Bit 4

SDRAM4

(Active/Inactive)

Bit 3

SDRAM3

(Active/Inactive)

Bit 2

SDRAM2

(Active/Inactive)

Bit 1

SDRAM1

(Active/Inactive)

Bit 0

SDRAM0

(Active/Inactive)

Byte 5: Control Register 5

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

SDRAM_F

(Active/Inactive)

Bit 3

SDRAM11

(Active/Inactive)

Bit 2

SDRAM10

(Active/Inactive)

Bit 1

SDRAM9

(Active/Inactive)

Bit 0

SDRAM8

(Active/Inactive)

CY28301

Document #: 38-07011 Rev. *C

Page 7 of 15

Byte 6: Vendor ID and Revision ID Register (Read-only)

Bit

Name

Default

Pin Description

Bit 7

Revision_ID3

Revision ID bit[3]

Bit 6

Revision_ID2

Revision ID bit[2]

Bit 5

Revision_ID1

Revision ID bit[1]

Bit 4

Revision_ID0

Revision ID bit[0]

Bit 3

Vendor_ID3

Bit[3] of Cypress's Vendor ID. This bit is Read-only.

Bit 2

Vendor_ID2

Bit[2] of Cypress's Vendor ID. This bit is Read-only.

Bit 1

Vendor _ID1

Bit[1] of Cypress's Vendor ID. This bit is Read-only.

Bit 0

Vendor _ID0

Bit[0] of Cypress's Vendor ID. This bit is Read-only.

Byte 7: Control Register 7

Bit

Pin#

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

24_48MHz_DRV

0 = Norm, 1 = High drive

Bit 5

48MHz_DRV

0 = Norm, 1 = High drive

Bit 4

Reserved

Bit 3

24_48MHz

(Active/Inactive)

Bit 2

48 MHz

(Active/Inactive)

Bit 1

Reserved

Bit 0

Reserved

Byte 8: Reserved Register

Bit

Name

Default

Pin Description

Bit 7

PCI_Skew1

PCI skew control
00 = Normal
01 = 500 ps
10 = Reserved
11 = +500 ps

Bit 6

PCI_Skew0

Bit 5

Reserved

Reserved. Write with `1'

Bit 4

Reserved

Reserved. Write with `1'

Bit 3

Reserved

Reserved. Write with `1'

Bit 2

Reserved

Reserved. Write with `1'

Bit 1

Reserved

Reserved. Write with `1'

Bit 0

Reserved

Byte 9: Reserved Register

Bit

Name

Default

Pin Description

Bit 7

SDRAM_DRV

SDRAM clock output drive strength
0 = Normal
1 = High Drive

Bit 6

PCI_DRV

PCI and AGP clock output drive strength
0 = Normal
1 = High drive

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

CY28301

Document #: 38-07011 Rev. *C

Page 8 of 15

Bit 1

Reserved

Bit 0

Reserved

Byte 10: Reserved Register

Bit

Name

Default

Description

Bit 7

CPU_Skew2

CPU skew control
000 = Normal
001 = 150 ps
010 = 300 ps
011 = 450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps

Bit 6

CPU_Skew1

Bit 5

CPU_Skew0

Bit 4

SDRAM_Skew2

SDRAM skew control
000 = Normal
001 = 150 ps
010 = 300 ps
011 = 450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps

Bit 3

SDRAM_Skew1

Bit 2

SDRAM_Skew0

Bit 1

AGP_Skew1

AGP skew control
00 = Normal
01 = 150 ps
10 = +150 ps
11 = +300 ps

Bit 0

AGP_Skew0

Byte 11: Reserved Register

Bit

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 12: Reserved Register

Bit

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 9: Reserved Register (continued)

Bit

Name

Default

Pin Description

CY28301

Document #: 38-07011 Rev. *C

Page 9 of 15

Byte 13: Reserved Register

Bit

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 14: Reserved Register

Bit

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 15: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Reserved. Write with `1'

Bit 0

Reserved

Reserved. Write with `1'

Byte 16: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Byte 17: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Reserved

CY28301

Document #: 38-07011 Rev. *C

Page 10 of 15

DC Electrical Characteristics

[2]

DC parameters must be sustainable under steady state (DC) conditions.

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Table 5. Frequency Selections through HW Strap Option and Serial Data Interface Data Bytes

Input Conditions

Output Frequency

FS1

FS0

CPU

SDRAM

3V66

PCI

APIC

SEL1

SEL0

66.6

100.0

66.6

33.3

16.6

100.0

66.6

33.3

16.6

133.3

66.6

33.3

16.6

133.3

100.0

66.6

33.3

16.6

Byte 17: Reserved Register (continued)

Bit

Pin#

Name

Default

Description

Absolute Maximum DC Power Supply

Parameter

Description

Min.

Max.

Unit

DDQ3

3.3V Core Supply Voltage

0.5

4.6

DDQ2

2.5V I/O Supply Voltage

0.5

3.6

Storage Temperature

150

°C

Absolute Maximum DC I/O

Parameter

Description

Min.

Max.

Unit

i/o3

3.3V Core Supply Voltage

0.5

4.6

i/o3

2.5V I/O Supply Voltage

0.5

3.6

ESD prot.

Input ESD Protection

2000

DC Operating Requirements

Parameter

Description

Condition

Min.

Max.

Unit

DD3

3.3V Core Supply Voltage

3.3V ±5%

3.135

3.465

DDQ3

3.3V I/O Supply Voltage

3.3V ±5%

3.135

3.465

DDQ2

2.5V I/O Supply Voltage

2.5V ±5%

2.375

2.625

DD3

3.3V ±5%

ih3

3.3V Input High Voltage

DD3

2.0

+ 0.3

il3

3.3V Input Low Voltage

0.3

0.8

Input Leakage Current

[3]

0 < V

DD3

µA

DDQ2

2.5V ±5%

oh2

2.5V Output High Voltage

= (1 mA)

2.0

ol2

2.5V Output Low Voltage

= (1 mA)

0.4

Note:

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

Input leakage current does not include inputs with pull-up or pull-down resistors.

CY28301

Document #: 38-07011 Rev. *C

Page 11 of 15

DDQ3

3.3V ±5%

oh3

3.3V Output High Voltage

= (1 mA)

ol3

3.3V Output Low Voltage

= (1 mA)

0.4

DDQ3

3.3V ±5%

poh3

PCI Bus Output High Voltage

= (1 mA)

2.4

pol3

PCI Bus Output Low Voltage

= (1 mA)

0.55

Input Pin Capacitance

xtal

Xtal Pin Capacitance

13.5

22.5

out

Output Pin Capacitance

Pin Inductance

Ambient Temperature

No airflow

°C

DC Operating Requirements (continued)

Parameter

Description

Condition

Min.

Max.

Unit

CY28301

Document #: 38-07011 Rev. *C

Page 12 of 15

AC Electrical Characteristics

[2]

(

= 0°C to +70°C, V

DDQ3

= 3.3V ±5%, V

DDQ2

= 2.5V ±5% f

XTL

= 14.31818 MHz)

Parameter

Description

66.6-MHz Host

100-MHz Host

133-MHz Host

Unit

Notes

Min.

Max.

Min.

Max.

Min.

Max.

CPUCLK
T

Period

Host/CPUCLK Period

15.0

15.5

10.0

10.5

7.5

8.0

HIGH

Host/CPUCLK High Time

5.2

N/A

3.0

N/A

1.87

N/A

LOW

Host/CPUCLK Low Time

5.0

N/A

2.8

N/A

1.67

N/A

RISE

Host/CPUCLK Rise Time

0.4

1.6

0.4

1.6

0.4

1.6

FALL

Host/CPUCLK Fall Time

0.4

1.6

0.4

1.6

0.4

1.6

SDRAM
T

Period

SDRAM CLK Period

10.0

10.5

10.0

10.5

10.0

10.5

HIGH

SDRAM CLK High Time

3.0

N/A

3.0

N/A

3.0

N/A

LOW

SDRAM CLK Low Time

2.8

N/A

2.8

N/A

2.8

N/A

RISE

SDRAM CLK Rise Time

0.4

1.6

0.4

1.6

0.4

1.6

FALL

SDRAM CLK Fall Time

0.4

1.6

0.4

1.6

0.4

1.6

APIC
T

Period

APIC CLK Period

60.0

64.0

60.0

N/A

60.0

64.0

HIGH

APIC CLK High Time

25.5

N/A

25.5

N/A

25.5

N/A

LOW

APIC CLK Low Time

25.3

N/A

25.30

N/A

25.30

N/A

RISE

APIC CLK Rise Time

0.4

1.6

0.4

1.6

0.4

1.6

FALL

APIC CLK Fall Time

0.4

1.6

0.4

1.6

0.4

1.6

3V66
T

Period

3V66 CLK Period

15.0

16.0

15.0

16.0

15.0

16.0

4, 8

HIGH

3V66 CLK High Time

5.25

N/A

5.25

N/A

5.25

N/A

LOW

3V66 CLK Low Time

5.05

N/A

5.05

N/A

5.05

N/A

RISE

3V66 CLK Rise Time

0.5

2.0

0.5

2.0

0.5

2.0

FALL

3V66 CLK Fall Time

0.5

2.0

0.5

2.0

0.5

2.0

PCI
T

Period

PCI CLK Period

30.0

N/A

30.0

N/A

30.0

N/A

4, 7

HIGH

PCI CLK High Time

12.0

N/A

12.0

N/A

12.0

N/A

LOW

PCI CLK Low Time

12.0

N/A

12.0

N/A

12.0

N/A

RISE

PCI CLK Rise Time

0.5

2.0

0.5

2.0

0.5

2.0

FALL

PCI CLK Fall Time

0.5

2.0

0.5

2.0

0.5

2.0

, tp

Output Enable Delay (All outputs)

1.0

10.0

1.0

10.0

1.0

10.0

, tp

Output Disable Delay
(All outputs)

1.0

10.0

1.0

10.0

1.0

10.0

stable

All Clock Stabilization from
Power-Up

Notes:

Period, jitter, offset, and skew measured on the rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.

The time specified is measured from when V

DDQ3

achieves its nominal operating level (typical condition V

DDQ3

= 3.3V) until the frequency output is stable

and operating within specifications.

RISE

and T

FALL

are measured as transitions through the threshold region V

= 0.4V and V

= 2.0V (1 mA) JEDEC specification.

HIGH

is measured at 2.0V for 2.5V outputs, and 2.4V for 3.3V outputs.

LOW

is measured at 0.4V for all outputs.

CY28301

Document #: 38-07011 Rev. *C

Page 13 of 15

Group Skew and Jitter Limits

Output Group

Pin-Pin Skew Max.

Cycle-Cycle Jitter

Duty Cycle

Nom. V

Skew, Jitter

Measure Point

CPU

175 ps

250 ps

45/55

2.5V

1.25V

SDRAM

250 ps

45/55

3.3V

1.5V

APIC

250 ps

500 ps

45/55

2.5V

1.25V

48MHz

250 ps

500 ps

45/55

3.3V

1.5V

3V66

175 ps

500 ps

45/55

3.3V

1.5V

PCI

500 ps

45/55

3.3V

1.5V

REF

N/A

1000 ps

45/55

3.3V

1.5V

Clock Output Wave

2.5V Clocking

3.3V Clocking

Test Point

Test Load

PERIOD

Duty Cycle

HIGH

2.0

1.25

0.4

LOW

RISE

FALL

LOW

RISE

FALL

PERIOD

Duty Cycle

HIGH

2.4

1.5

0.4

Output
Buffer

Interface

Figure 1. Output Buffer

CY28301

Document #: 38-07011 Rev. *C

Page 14 of 15

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Drawing and Dimension

Intel is a registered trademark of Intel Corporation. All product or company names mentioned in this document are the trademarks
of their respective holders.

Ordering Information

Ordering Code

Package Type

Operating Range

CY28301PVC

56-pin SSOP (300 mils)

Commercial, 0°C to 70°C

CY28301PVCT

56-pin SSOP (300 mils) - Tape and Reel

Commercial, 0°C to 70°C

56-Lead Shrunk Small Outline Package O56

51-85062-*C

CY28301

Document #: 38-07011 Rev. *C

Page 15 of 15

Document History Page

Document Title: CY28301 Frequency Generator for Intel

Integrated Chipset

Document Number: 38-07011

REV.

ECN

NO.

Issue

Date

Orig. of

Change

Description of Change

106533

06/27/01

IKA

Change from Spec #: 38-01096 to 38-07011
Changed I2C to SMBus and Updated Byte Tables

109365

11/06/01

IKA

Revise AC and DC Tables

118785

09/25/02

DMG

Corrected the spread spectrum values in Bits 0 to 2 in Byte 0 (Control
register 0) table to match the device.
Changed the Package Drawing and Dimension to CY Standard.
Added the tape and reel option in the ordering information table.

122717

12/21/02

RBI

Added power up requirements to operating conditions information.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY28301PVCT

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY28301PVCT