FTG for Mobile VIATM PL133T and PLE133T Chipsets
CY28317-2
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07094 Rev. *B
Revised December 26, 2002
17-2
Features
Single-chip system frequency synthesizer for mobile
VIA PL133T and PLE133T chipsets
Programmable clock output frequency with less than
1 MHz increment
Integrated fail-safe Watchdog Timer for system
recovery
Automatic switch to HW-selected or SW-programmed
clock frequency when Watchdog Timer time-out occurs
System RESET generation capability after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
Support SMBus byte Read/Write and block Read/ Write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength for SDRAM and PCI
output clocks
Programmable output skew for CPU, PCI and SDRAM
Maximized EMI Suppression using Cypress's Spread
Spectrum technology
Available in 48-pin SSOP and TSSOP packages
Key Specifications
CPU to CPU Output Skew:.......................................... 175 ps
PCI to PCI Output Skew: ............................................. 500 ps
Block Diagram
Pin Configuration
Note:
1.
Signals marked with `*' have internal pull-up resistors.
[1]
VDD_REF
REF0
PCI0_F/FS4*
XTAL
PLL Ref Freq
PLL 1
X2
X1
REF1/FS2*
VDD_PCI
PCI2:6
48MHz/FS0*
24_48MHz/FS1*
PLL2
2,3,4
OSC
VTT_PWRGD#
VDD_48MHz
SMBus
SDATA
Logic
SCLK
SDRAM0:6
SDRAMIN
7
VDD_SDRAM
PCI1/FS3*
CPU0:1, CPUT, CPUC
2
GND_CPU
*FS2/REF1
REF0
VTT_PWRGD#
VDD_REF
GND_REF
X1
X2
VDD_PCI
*FS4/PCI0_F
*FS3/PCI1
GND_PCI
PCI2
PCI3
PCI4
PCI5
PCI6
SDRAMIN
*CPU_STOP#
*PCI_STOP#
*PD#
*MULT_SEL
GND_48MHz
SDATA
CY
28
31
7-
2
CPU0
CPU1
VDD_CPU_2.5
VDD_CPU_3.3
CPUT
CPUC
GND_CPU
RST#
IREF
SDRAM6
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*
SCLK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Logic
Reset
RST#
IREF
MULT_SEL
PCI_STOP#
CPU_STOP#
PD#
CY28317-2
Document #: 38-07094 Rev. *B
Page 2 of 21
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
CPU0, CPU1
48, 47
O
CPU Clock Output 0 through 1: CPU clocks for processor and chipset.
CPUT, CPUC
44, 43
O
Differential CPU Clock Output: Differential CPU clocks for processor.
PCI2:6
13, 14, 15,
16, 17
O
PCI Clock Outputs 2 through 6: 3.3V 33-MHz PCI clock outputs. Frequency
is set by FS0:4 inputs or through serial data interface.
PCI1/FS3
11
I/O
Fixed PCI Clock Output/Frequency Select 3: 3.3V PCI clock outputs. As an
output, the frequency is set by FS0:4 inputs or through serial data interface. This
pin also serves as a power-on strap option to determine device operating fre-
quency, as described in Table 6.
PCI0_F/FS4
10
I/O
Fixed PCI Clock Output/Frequency Select 4: 3.3V Free-running PCI clock
outputs. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 6.
RST#
41
O
(open-
drain)
Reset# Output: Open drain system reset output.
48MHz/FS0
27
I/O
48-MHz Output/Frequency Select 0: 3.3V 48-MHz non-spread spectrum out-
put. This pin also serves as a power-on strap option to determine device oper-
ating frequency as described in Table 6.
24_48MHz/
FS1
26
I/O
24_48MHz Output/Frequency Select 1: 3.3V 24- or 48-MHz non-spread spec-
trum output. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 6.
REF1/FS2
2
I/O
Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output
clock. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 6.
REF0
3
O
Reference Clock Output 0: 3.3V 14.318-MHz output clock.
SDRAMIN
18
I
SDRAM Buffer Input Pin: Reference input for SDRAM buffer.
SDRAM0:6
37, 36, 34,
33, 31, 30, 39
O
SDRAM Outputs: These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input.
SCLK
25
I
Clock pin for SMBus circuitry.
SDATA
24
I/O
Data pin for SMBus circuitry.
X1
7
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
X2
8
O
Crystal Connection: An output connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
PD#
21
I
Power Down Control: LVTTL-compatible input that places the device in power-
down mode when held LOW.
CPU_STOP#
19
I
CPU Output Control: 3.3V LVTTL compatible input that stops CPU0, CPU1,
CPUT, and CPUC when held LOW.
PCI_STOP#
20
I
PCI Output Control: 3.3V LVTTL compatible input that stop PCI1:6 when held
LOW.
IREF
40
I
Current Reference Input: Current reference for differential CPU output.
MULT_SEL
22
I
CPUT and CPUC Output Control: Control the current multiplier for differential
CPU output. Set this pin LOW for 1.0V output swing and set this pin HIGH for
0.7V output swing.
VTT_PWRGD#
4
I
VTT_PWRGD#: 3.3V LVTTL compatible input that controls the FS0:4 to be
latched and enables all outputs. CY28316 will sample the FS0:4 inputs and
enable all clock outputs after all the VDD become valid and VTT_PWRGD# is
held LOW.
CY28317-2
Document #: 38-07094 Rev. *B
Page 3 of 21
VDD_REF,
VDD_PCI,
VDD_SDRAM,
VDD_48MHz
VDD_CPU_3.3
5, 9, 28, 29,
35, 45
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Con-
nect to 3.3V supply.
VDD_CPU_2.5
46
P
Power Connection: Power supply for CPU outputs. Connect to 2.5V supply.
GND_REF,
GND_PCI,
GND_SDRAM,
GND_48MHz,
GND_CPU
1, 6, 12, 23,
32, 38, 42
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Pin Definitions
(continued)
Pin Name
Pin No.
Pin Type
Pin Description
Table 1. Swing Select Functions
Mult0
Board Target
Trace/Term Z
Reference R, IREF=
VDD/(3*Rr)
Output Current
V
OH
@ Z
0
60
Rr = 221 1%
IREF = 5.00 mA
I
OH
= 4*IREF
1.0V @ 50
1
50
Rr = 475 1%
IREF = 2.32 mA
I
OH
= 6*IREF
0.7V @ 50
CY28317-2
Document #: 38-07094 Rev. *B
Page 4 of 21
Serial Data Interface
The CY28317-2 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write and block Read operations from
the controller. For block Write/Read operations, the bytes must
be accessed in sequential order from lowest to highest byte
with the ability to stop after any complete byte has been trans-
ferred. For byte/word Write and byte Read operations, the sys-
tem controller can access individual indexed bytes. The offset
of the indexed byte is encoded in the command code.
The definition for the command code is defined as shown in
Table 2.
Table 2. Command Code Definition
Bit
Descriptions
7
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
6:0
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at `0000000'.
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 bits
`00000000' stands for block operation
11:18
Command Code 8 bits
`00000000' stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte count 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29:36
Data byte 0 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 8 bits
30:37
Byte count from slave 8 bits
46
Acknowledge from slave
38
Acknowledge
...
Data byte N/Slave acknowledge...
39:46
Data byte from slave 8 bits
...
Data byte N 8 bits
47
Acknowledge
...
Acknowledge from slave
48:55
Data byte from slave 8 bits
...
Stop
56
Acknowledge
...
Data bytes from slave/Acknowledge
...
Data byte N from slave - 8 bits
...
Not acknowledge
...
Stop
CY28317-2
Document #: 38-07094 Rev. *B
Page 5 of 21
Table 4. Word Read and Word Write Protocol
Word Write Protocol
Word Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
11:18
Command Code 8 bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte low 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29:36
Data byte high 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38
Stop
30:37
Data byte low from slave 8 bits
38
Acknowledge
39:46
Data byte high from slave 8 bits
47
Not acknowledge
48
Stop
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address 7 bits
2:8
Slave address 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
11:18
Command Code 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address 7 bits
29
Stop
28
Read
29
Acknowledge from slave
30:37
Data byte from slave 8 bits
38
Not acknowledge
39
Stop
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