1:4 Clock Fanout Buffer
ComLinkTM Series
CY2DP814
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07060 Rev. *B
Revised December 15, 2002
Features
Low voltage operation
V
DD
= 3.3V
1:4 fanout
Single-input configurable for LVDS, LVPECL, or LVTTL
Four differential pairs of LVPECL outputs
Drives 50-ohm load
Low input capacitance
Low output skew
Low propagation delay
-- Typical (tpd < 4 ns)
Industrial versions available
Available packages include TSSOP, SOIC
Description
The Cypress CY2 series of network circuits are produced
using advanced 0.35-micron CMOS technology, achieving the
industry's fastest logic.
The Cypress CY2DP814 fanout buffer features a single LVDS-
or a single LVPECL-compatible input and four LVPECL output
pairs.
Designed for data communications clock management appli-
cations, the fanout from a single input reduces loading on the
input clock.
The CY2DP814 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVDS-based clock signals. The Cypress CY2DP814 has
configurable input between logic families. The input can be
selectable for an LVPECL/LVTTL or LVDS signal, while the
output drivers support LVPECL capable of driving 50-ohm
lines.
Block Diagram
Pin Configuration
OUTPUT
IN+ 6
IN- 7
16 Q1A
15 Q1B
14 Q2A
13 Q2B
10 Q4A
9 Q4B
12 Q3A
11 Q3B
LVDS /
LVPECL /
LVTTL
CONFIG 2
EN1 1
EN2 8
LVPECL
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CY2DP814
16 pin TSSOP / SOIC
EN1
CONFIG
VDD
VDD
IN+
IN-
EN2
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
ComLinkTM Series
CY2DP814
Document #: 38-07060 Rev. *B
Page 2 of 9
Pin Description
Pin Number
Pin Name
Pin Standard Interface
Description
6, 7
IN+, IN
Configurable
Differential input pair or single line. LVPECL default.
See CONFIG below.
2
CONFIG
LVTTL/LVCMOS
Converts inputs from the default
LVPECL/LVDS (logic = 0)
to LVTTL/LVCMOS (logic = 1).
See Figure 6 and Figure 7 for additional information
1, 8
EN1, EN2
LVTTL/LVCMOS
Enable/disable logic. See Function Table below for
details.
16, 15, 14, 13, 12, 11, 10, 9
Q1A, Q1B,
Q2A, Q2B,
Q3A, Q3B,
Q4A, Q4B
LVPECL
Differential outputs.
3, 4
V
DD
POWER
Positive supply voltage.
5
GND
POWER
Ground.
ComLinkTM Series
CY2DP814
Document #: 38-07060 Rev. *B
Page 3 of 9
Maximum Ratings
[1][2]
Storage Temperature: .................................65
C to +150
C
Ambient Temperature:................................... 40
C to +85
C
Supply Voltage to Ground Potential
(Inputs and V
CC
only)....................................... 0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only) ........................................ 0.3V to V
DD
+ 0.3V
DC Input Voltage ................................... 0.3V to V
DD
+ 0.3V
DC Output Voltage................................. 0.3V to V
DD
+ 0.9V
Power Dissipation........................................................ 0.75W
Table 1. EN1 EN2 Function Table
Enable Logic
Input
Outputs
EN1
EN2
IN+
IN
QnA
QnB
H
H
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
L
H
X
X
Z
Z
Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS
CONFIG Pin 2 Binary Value
Input Receiver Family
Input Receiver Type
1
LVTTL in LVCMOS
Single ended, non-inverting, inverting, void of bias resistors.
0
LVDS
Low voltage differential signaling
LVPECL
Low voltage pseudo (positive) emitter coupled logic
Table 3. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
LVTTL/LVCMOS INPUT LOGIC
Input Condition
Input Logic
Output Logic Q pins
Ground
IN- Pin 7
IN+ Pin 6
Input
True
V
CC
IN- Pin 7
IN+ Pin 6
Input
Invert
Ground
IN+ Pin 6
IN- Pin 7
Input
Invert
V
CC
IN+ Pin 6
IN- Pin 7
Input
True
Table 4. Power Supply Characteristics
Parameter
Description
Test Conditions
Min.
Typ. Max.
Unit
I
CCD
Dynamic Power Supply Current V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs Loaded
1.5
2.0
mA/MHz
I
C
Total Power Supply Current
V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs Loaded,
fL= 100 MHz
90
100
mA
Table 5. D.C. Electrical Characteristics: 3.3VLVDS Input
Parameter
Description
Conditions
Min. Typ. Max. Unit
V
ID
Magnitude of Differential Input Voltage
100
600
mV
V
IC
Common-Mode of Differential Input Voltage
IV
ID
I (min. and max.)
IVIDI
/2
2.4
(IVIDI /2)
V
I
IH
Input High Current
V
DD
= Max.
V
IN
= V
DD
10
20
uA
I
IL
Input Low Current
V
DD
= Max.
V
IN
= V
SS
0
20
uA
I
I
Input High Current
V
DD
= Max., V
IN
= V
DD
(max.)
20
uA
Notes:
1.
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
ComLinkTM Series
CY2DP814
Document #: 38-07060 Rev. *B
Page 4 of 9
Table 6. D.C. Electrical Characteristics: 3.3VLVPECL Input
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
I
V
ID
I
Differential Input Voltage p-p
Guaranteed Logic High Level
400
2600
mV
VCM
Common-mode Voltage
1650
2250
mV
I
IH
Input High Current
V
DD
= Max.
V
IN
= V
DD
10
20
uA
I
IL
Input Low Current
V
DD
= Max.
V
IN
= V
SS
10
20
uA
I
I
Input High Current
V
DD
= Max.,
V
IN
=
V
DD
(max.)
20
uA
Table 7. D.C Electrical Characteristics: 3.3VLVTTL/LVCMOS Input
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
V
IH
Input High Voltage
Guaranteed Logic High Level
2
V
V
IL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
I
IH
Input High Current
V
DD
= Max.
V
IN
= 2.7V
1
uA
I
IL
Input Low Current
V
DD
= Max.
V
IN
= 0.5V
1
uA
I
I
Input High Current
V
DD
= Max.,
V
IN
=
V
DD
(max.)
20
uA
V
IK
Clamp Diode Voltage
V
DD
= Min.,
I
IN
= 18 mA
0.7
1.2
V
V
H
Input Hysteresis
80
mV
Table 8. D.C Electrical Characteristics: 3.3VLVPECL Output
Parameter
Description
Condition
Min.
Typ.
Max. Unit
I
V
OD
I
Driver Differential Output Voltage p-p
V
DD
= Min.,
V
IN
=
V
IH
or
V
IL
RL = 50 ohm
1000
3600
mV
I
V
OC
I
Driver common-mode p-p
V
DD
= Min.,
V
IN
=
V
IH
or
V
IL
RL = 50 ohm
226
mV
Rise Time
Differential 20% to 80%
CL10 pF RL and CL to
G
ND
RL = 50 ohm
300
800
pS
Fall Time
V
OH
Output High Voltage
V
DD
= Min.,
V
IN
=
V
IH
or
V
IL
I
OH
= 12 mA
2.1
3.0
V
V
OL
Output Low Voltage
User-defined (see Figure 1)
V
I
OS
Short Circuit Current
V
DD
= Max.,
V
OUT
=
G
ND
125
150
mA
Table 9. AC Switching Characteristics @ 3.3V V
DD
= 3.3V 5%, Temperature = 40
C to +85
C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IN [+,-] to Q[A,B] Data & Clock Speed
t
PLH
Propagation DelayLow to High
V
OD
= 100 mV
3
4
5
nS
t
PHL
Propagation DelayHigh to Low
3
4
5
nS
t
PD
Propagation Delay
3
4
5
ns
EN [1,2] to Q[A,B] Control Speed
t
PE
Enable (EN) to functional operation
6
nS
Tpd
Functional operation to Disable
5
nS
t
SK(0)
Output Skew: Skew between outputs of the same package (in phase)
0.2
nS
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
t
PLH
)
0.2
nS
t
SK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type. Same
input signal level and output load.
V
ID
= 100 mV
1
nS
ComLinkTM Series
CY2DP814
Document #: 38-07060 Rev. *B
Page 5 of 9
Notes:
3.
RL = 50 ohm
1%; Zline = 50 ohm 6
=
.
4.
CL includes instrumentation and fixture capacitance within 6 mm of the UT.
5.
TPA and B are used for prop delay and rise/fall measurements. T
PC
is used for V
OC
measurements only and otherwise connected to V
DD
2.
6.
When measuring Tr/Tf, tpd, V
OD
point T
PC
is held at V
DD
2.0V.
7.
LVCMOS/LVTTL single-ended input value. Ground either input: when on the B side, non-inversion takes place. If A side is grounded, the signal becomes the
complement of the input on B side. See Table 3.
Table 10. High-frequency Parametrics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Maximum Frequency
V
DD
= 3.3V
50% Duty Cycle tW(5050)
Standard Load Circuit
450
MHz
Fmax(20)
Maximum Frequency
V
DD
= 3.3V
20% Duty Cycle tW(2080)
LVPECL Input
Vin = V
IH
(Max.)/V
IL
(Min.)
Vout = V
OH
(Min.)/V
OL
(Max.) (Limit)
175
MHz
TW
Minimum Pulse
V
DD
= 3.3V
LVPECL Input
Vin = V
IH
(Max.)/V
IL
(Min.) F = 100 MHz
Vout = V
OH
(Min.)/V
OL
(Max.).(Limit)
900 pS
Q
Q
VDD
VDD - 2V
Device concept
User Defined
VTT & RTT
Figure 1. Differential PECL Output
8 0 %
2 0 %
0 V D if f e r e n tia l
V 0 Y -
V 0 Z
t
R
t
F
1.4 V
1.0 V
1.4 V
1.0 V
0 V D if f e r e n tia l
0 V D if f e r e n tia l
1 .2 V C M
1 .2 V C M
V 1A
V 1B
V 0Y
V 0Z
T
P L H
T
P H L
En 1
En 2
T P A
T PC
TP B
5 0
5 0
G N D
15 0
15 0
S tand ard Te rm in ation
P u lse
G e ne ra to r
A
B
1 0 p F
V D D -2 V
Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time
[3, 4, 5, 6, 7]
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