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1:8 Clock Fanout Buffer
ComLinkTM Series
CY2DP818
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07061 Rev. *A
Revised July 9, 2002
Features
Low-voltage operation V
DD
= 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50-ohm load
Low input capacitance
Low output skew
Low propagation delay Typical (tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at
350 MHz700 Mbps
Description
This Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry's fastest logic.
The Cypress CY2DP818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVPECL
output pairs.
Designed for data-communications clock-management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVPECL-based clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the Inconfig pin for single ended
or differential input.
Block Diagram
Pin Configuration
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
38-pin TSSOP
GND
VDD
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
Q4A
GND
VDD
GND
GND
VDD
InConfig
INPUT A
INPUT B
GND
GND
CY
2DP
818
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ComLinkTM Series
CY2DP818
Document #: 38-07061 Rev. *A
Page 2 of 8
Maximum Ratings
[1]
Storage Temperature: ................................65
C to + 150
C
Ambient Temperature:................................... 40
C to +85
C
Supply Voltage to Ground Potential
(Inputs and V
CC
only)....................................... 0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only) ........................................ 0.3V to V
DD
+ 0.3V
DC Input Voltage ................................... 0.3V to V
DD
+ 0.3V
DC Output Voltage................................. 0.3V to V
DD
+ 0.9V
Power Dissipation........................................................ 0.75W
Notes:
1.
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Pin Description
Pin Number
Pin Name
Pin Standard Interface
Description
1, 9,12,18,19,20,38
GND
POWER
Ground
2,3,4,5,6,8, 13,14,15,16,17,29
VDD
POWER
Power Supply
10,11
Input A, Input B
Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
Differential input pair or single line.
LVPECL/LVDS default. See InConfig,
below.
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
LVPECL
Differential Outputs
7
InConfig
LVTTL/LVCMOS
Converts inputs from the default
LVPECL/LVDS (logic = 0)
To LVTTL/LVCMOS (logic = 1)
See Figure 4 and Figure 5 for additional
Information
Table 1. Power Supply Characteristics
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
ICCD
Dynamic Power Supply Current
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open
1.5
2.0
mA/MHz
IC
Total Power Supply Current
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs 50 ohms
fL=100 MHz
350
mA
IC Core
Core current when output loads are
disabled
V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs
Disabled, not connected to VTT
fL=100 MHz
50
mA
Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS
INCONFIG
Pin 7
Binary Value
Input Receiver Family
Input Receiver Type
1
LVTTL in LVCMOS
Single-ended, non-inverting, inverting, void of bias resistors
0
LVDS
Low-voltage differential signaling
LVPECL
Low-voltage pseudo (positive) emitter coupled logic
ComLinkTM Series
CY2DP818
Document #: 38-07061 Rev. *A
Page 3 of 8
Table 3. Function Control of the TTL Input Logic used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition
Input Logic
Output Logic Q Pins, Q1A or Q1
Ground
Input B () Pin 11
Input A (+) Pin 10
Input
True
VCC
Input B () Pin 11
Input A (+) Pin 10
Input
Invert
Ground
Input A (+) Pin 10
Input B () Pin 11
Input
Invert
VCC
Input A (+) Pin 10
Input B () Pin 11
Input
True
Table 4. DC Electrical Characteristics: 3.3VLVDS Input
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
ID
Magnitude of Differential Input Voltage
100
600
mV
V
IC
Common-mode of Differential Input
VoltageIV
ID
I (min. and max.)
IVIDI/2 2.4(IVIDI/2)
V
V
IH
Input High Voltage
Guaranteed Logic High Level
2
V
V
IL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
I
IH
Input High Current
V
DD
= Max.
V
IN
= V
DD
10
20
A
I
IL
Input Low Current
V
DD
= Max.
V
IN
= V
SS
10
20
A
I
I
Input High Current
V
DD
= Max., V
IN
= V
DD
(Max.)
20
A
Table 5. DC Electrical Characteristics: 3.3VLVPECL Input
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
ID
Differential Input Voltage p-p
Guaranteed Logic High Level
400
2600
mV
V
IH
Input High Voltage
Guaranteed Logic High Level
2.15
2.4
V
V
IL
Input Low Voltage
Guaranteed Logic Low Level
1.5
1.8
V
I
IH
Input High Current
V
DD
= Max.
V
IN
= V
DD
10
20
A
I
IL
Input Low Current
V
DD
= Max.
V
IN
= V
SS
10
20
A
I
I
Input High Current
V
DD
= Max., V
IN
= V
DD
(Max.)
20
A
V
CM
Common-mode Voltage
225
mV
Table 6. DC Electrical Characteristics: 3.3VLVTTL/LVCMOS Input
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
V
IH
Input High Voltage
Guaranteed Logic High Level
2
V
V
IL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
I
IH
Input High Current
V
DD
= Max
V
IN
= 2.7V
1
A
I
IL
Input Low Current
V
DD
= Max
V
IN
= 0.5V
1
A
I
I
Input High Current
V
DD
= Max., V
IN
= V
DD
(Max)
20
A
V
IK
Clamp Diode Voltage
V
DD
= Min., I
IN
= 18mA
0.7
1.2
V
V
H
Input Hysteresis
80
mV
ComLinkTM Series
CY2DP818
Document #: 38-07061 Rev. *A
Page 4 of 8
Table 7. DC Electrical Characteristics: 3.3VLVPECL Output
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
OD
Driver Differential Output
voltage p-p
V
DD
= Min., V
IN
= V
IH
or V
IL
RL = 50 ohm
1000
3600
mV
V
OC
Driver common-mode p-p V
DD
= Min., V
IN
= V
I
H or V
IL
RL = 50 ohm
300
mV
Rise Time
Differential 20% to 80%
CL10 pF RL and CL to GND
RL = 50 ohm
300
1200
ps
Fall Time
V
OH
Output High Voltage
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= 12 mA
2.1
3.0
V
V
OL
Output Low Voltage
V
DD
= Min., V
IN
= V
IH
or V
IL
User defined by VTT RTT.
0.8
1.3
V
I
OS
Short Circuit Current
V
DD
= Max, V
OUT
= GND
125
150
mA
Table 8. AC Switching Characteristics @ 3.3 V (V
DD
= 3.3V 5%, Temperature = 40C to +85C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
t
PLH
Propagation Delay Low to High
V
OD
= 100 mV
3
4
5
ns
t
PHL
Propagation Delay High to Low
3
4
5
ns
T
PE
Enable (EN) to functional operation
6
ns
T
PD
Functional operation to Disable
5
ns
t
SK(0)
Output Skew: Skew between outputs of the same package (in phase)
0.2
ns
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
t
PLH
)
0.2
ns
t
SK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type. Same
input signal level and output load.
V
ID
= 100 mV
1
ns
Driver Design
Table 9. High-frequency Parametrics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Maximum frequency
V
DD
= 3.3V
45%55% duty cycle
Standard load circuit
350
MHz
ComLinkTM Series
CY2DP818
Document #: 38-07061 Rev. *A
Page 5 of 8
Notes:
2.
All input pulses are supplied by a frequency generator with the following characteristics: t
R
and t
F
1 ns; pulse rerate = 50 Mpps; pulse width = 10
0.2 ns.
3.
RL = 50 ohm
1%; Zline = 50 ohm 6".
4.
CL includes instrumentation and fixture capacitance within 6 mm of the UT.
5.
TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to V
DD
2.
8 0 %
2 0 %
0 V D iffe re n tia l
V 0 Y -
V 0 Z
t
R
t
F
1.4 V
1.0 V
1.4 V
1.0 V
0 V D iffe re n tia l
0 V D iffe re n tia l
1 .2 V C M
1 .2 V C M
V1A
V1B
V0Y
V0Z
T
P L H
T
P H L
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
10pF
VDD-2V
Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time
[2,3,4,5]
2.0V
1.6V
V
I(A)
V
I(B)
Next Device
VOD
VOC
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
Figure 2. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage
[2,3,4,5]
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