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1-Mbit (64K x 16) Static RAM
CY62126DV30
MoBL
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05230 Rev. *E
Revised February 2, 2005
Features
Very high speed: 45 ns
Wide voltage range: 2.2V to 3.6V
Pin compatible with CY62126BV
Ultra-low active power
-- Typical active current: 0.85 mA @ f = 1 MHz
-- Typical active current: 5 mA @ f = f
MAX
Ultra-low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
Also available in Lead-free packages
Functional Description
[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery LifeTM (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array
I/O
0
I/O
7
R
O
W
DE
CO
DE
R
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
2048 x 512
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
I/O
15
CE
WE
BLE
BHE
A
0
A
1
A
9
A
10
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 2 of 11
Pin Configurations
[2, 3]
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
0
BHE
NC
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
NC
DNU
V
CC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
NC
A
4
A
3
OE
V
SS
A
5
I/O
15
A
2
CE
I/O
2
I/O
0
I/O
1
BHE
NC
A
1
A
0
18
17
20
19
I/O
3
27
28
25
26
22
21
23
24
NC
V
SS
I/O
6
I/O
4
I/O
5
I/O
7
A
6
A
7
BLE
V
CC
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
A
8
A
9
A
10
A
11
Product Portfolio
Product
V
CC
Range (V)
Speed (ns)
Power Dissipation
Operating, I
CC
(mA)
Standby, I
SB2
(
A)
f = 1 MHz
f = f
MAX
Min.
Typ.
Max.
Typ.
[4]
Max.
Typ.
[4]
Max.
Typ.
[4]
Max.
CY62126DV30L
2.2
3.0
3.6
45
0.85
1.5
6.5
13
1.5
5
CY62126DV30LL
45
0.85
1.5
6.5
13
1.5
4
CY62126DV30L
2.2
3.0
3.6
55
0.85
1.5
5
10
1.5
5
CY62126DV30LL
55
0.85
1.5
5
10
1.5
4
CY62126DV30L
2.2
3.0
3.6
70
0.85
1.5
5
10
1.5
5
CY62126DV30LL
70
0.85
1.5
5
10
1.5
4
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or V
SS
to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25C.
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65C to +150C
Ambient Temperature with
Power Applied.............................................55C to +125C
Supply Voltage to Ground
Potential ...........................................................
-0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State
[5.]
...................................
-0.3V to V
CC
+ 0.3V
DC Input Voltage
[5]
................................
-0.3V to V
CC
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature (T
A
)
V
CC
[6.]
Industrial
-40C to +85C
2.2V to 3.6V
DC Electrical Characteristics
(Over the Operating Range)
Parameter Description
Test Conditions
CY62126DV30-45
CY62126DV30-55 CY62126DV30-70
Unit
Min. Typ.
[4]
Max. Min. Typ.
[4]
Max. Min Typ.
[4]
Max.
V
OH
Output HIGH
Voltage
2.2 < V
CC
< 2.7 I
OH
=
-0.1 mA 2.0
2.0
2.0
V
2.7 < V
CC
< 3.6 I
OH
=
-1.0 mA 2.4
2.4
2.4
V
OL
Output LOW
Voltage
2.2 < V
CC
< 2.7 I
OL
= 0.1 mA
0.4
0.4
0.4
V
2.7 < V
CC
< 3.6 I
OL
= 2.1 mA
0.4
0.4
0.4
V
IH
Input HIGH
Voltage
2.2 < V
CC
< 2.7
1.8
V
CC
+ 0.3
1.8
V
CC
+ 0.3
1.8
V
CC
+ 0.3
V
2.7 < V
CC
< 3.6
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
V
IL
Input LOW
Voltage
2.2 < V
CC
< 2.7
-0.3
0.6
-0.3
0.6
-0.
3
0.6
V
2.7 < V
CC
< 3.6
-0.3
0.8
-0.3
0.8
-0.
3
0.8
I
IX
Input
Leakage
Current
GND < V
I
< V
CC
-1
+1
-1
+1
-1
+1
A
I
OZ
Output
Leakage
Current
GND < V
O
< V
CC
, Output
Disabled
-1
+1
-1
+1
-1
+1
A
I
CC
V
CC
Operating
Supply
Current
f = f
MAX
= 1/t
RC
V
CC
= 3.6V,
I
OUT
= 0 mA,
CMOS level
6.5
13
5
10
5
10
mA
f = 1 MHz
0.85
1.5
0.85
1.5
0.85
1.5
I
SB1
Automatic
CE
Power-down
Current
-
CMOS Inputs
CE > V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V, V
IN
< 0.2V,
f = f
MAX
(Address and Data
Only),
f = 0 (OE, WE, BHE and BLE)
L
1.5
5
1.5
5
1.5
5
A
LL
1.5
4
1.5
4
1.5
4
I
SB2
Automatic
CE
Power-down
Current
-
CMOS Inputs
CE > V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V,
f = 0, V
CC
= 3.6V
L
1.5
5
1.5
5
1.5
5
A
LL
1.5
4
1.5
4
1.5
4
Notes:
5. V
IL(min.)
=
-2.0V for pulse durations less than 20 ns., V
IH(max.)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
6. Full device operation requires linear ramp of V
CC
from 0V to V
CC(min)
& V
CC
must be stable at V
CC(min)
for 500
s.
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 4 of 11
AC Test Loads and Waveforms
[8]
Capacitance
[7]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz
V
CC
= V
CC(typ)
8
pF
C
OUT
Output Capacitance
8
pF
Thermal Resistance
Parameter
Description
Test Conditions
TSOP FBGA
Unit
JA
Thermal Resistance (Junction to Ambient)
[7]
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
55
76
C/W
JC
Thermal Resistance (Junction to Case)
[7]
12
11
C/W
Data Retention Characteristics
Parameter
Description
Conditions
Min.
Typ
.[4]
Max.
Unit
V
DR
V
CC
for Data Retention
1.5
V
I
CCDR
Data Retention Current
V
CC
=1.5V, CE > V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
L
4
A
LL
3
t
CDR
[7]
Chip Deselect to Data
Retention Time
0
ns
t
R
[9]
Operation Recovery Time
100
s
Notes:
7. Tested initially and after any design or proces changes that may affect these parameters.
8. Test condition for the 45 ns part is a load capacitance of 30 pF
9. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
>100
s.
V
CC
Typ
V
CC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
Parameters
2.5V
3.0V
Unit
R1
16600
1103
Ohms
R2
15400
1554
Ohms
R
TH
8000
645
Ohms
V
TH
1.2
1.75
Volts
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 5 of 11
Data Retention Waveform
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Characteristics
(Over the Operating Range)
[10]
Parameter
Description
CY62126DV30-45
[8]
CY62126DV30-55 CY62126DV30-70
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
45
55
70
ns
t
AA
Address to Data Valid
45
55
70
ns
t
OHA
Data Hold from Address Change
10
10
10
ns
t
ACE
CE LOW to Data Valid
45
55
70
ns
t
DOE
OE LOW to Data Valid
25
25
35
ns
t
LZOE
OE LOW to Low Z
[11]
5
5
5
ns
t
HZOE
OE HIGH to High Z
[11,
12]
15
20
25
ns
t
LZCE
CE LOW to Low Z
[11]
10
10
10
ns
t
HZCE
CE HIGH to High Z
[11,
12]
20
20
25
ns
t
PU
CE LOW to Power-up
0
0
0
ns
t
PD
CE HIGH to Power-down
45
55
70
ns
t
DBE
BLE/BHE LOW to Data Valid
25
25
35
ns
t
LZBE
BLE/BHE LOW to Low Z
[11]
5
5
5
ns
t
HZBE
BLE/BHE HIGH to High-Z
[11,
12]
15
20
25
ns
Write Cycle
[13]
t
WC
Write Cycle Time
45
55
70
ns
t
SCE
CE LOW to Write End
40
40
60
ns
t
AW
Address Set-up to Write End
40
40
60
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
35
40
50
ns
t
BW
BLE/BHE LOW to Write End
40
40
60
ns
t
SD
Data Set-up to Write End
25
25
30
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
HZWE
WE LOW to High Z
[11,
12]
15
20
25
ns
t
LZWE
WE HIGH to Low Z
[11]
10
10
5
ns
Notes:
10. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
.
12. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 6 of 11
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
Read Cycle No. 2 (OE Controlled)
[15, 16]
Notes:
14. Device is continuously selected. OE, CE = V
IL
, BHE, BLE = V
IL
.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE
t
LZOE
ADDRESS
t
DOE
t
LZOE
t
DBE
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 7 of 11
Write Cycle No. 1 (WE Controlled
[12, 13,
16, 17, 18]
Write Cycle No. 2 (CE Controlled)
[12, 13,
16, 17, 18]
Notes:
17. Data I/O is high-impedance if OE = V
IH
.
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE 19
BHE/BLE
t
BW
t
SCE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 19
BHE/BLE
t
BW
t
SA
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW)
[17, 18]
Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)
[17, 18]
Switching Waveforms
(continued)
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATAI/O
NOTE 19
t
BW
BHE/BLE
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
CE
WE
DATA
IN
VALID
NOTE 19
t
BW
BHE/BLE
t
SCE
t
PWE
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 9 of 11
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect/Power-Down
Standby (I
SB
)
L
X
X
H
H
High Z
Output Disabled
Active (I
CC
)
L
H
L
L
L
Data Out (I/O
O
I/O
15
)
Read
Active (I
CC
)
L
H
L
H
L
Data Out (I/O
O
I/O
7
);
I/O
8
I/O
15
in High Z
Read
Active (I
CC
)
L
H
L
L
H
Data Out (I/O
8
I/O
15
);
I/O
0
I/O
7
in High Z
Read
Active (I
CC
)
L
H
H
L
L
High Z
Output Disabled
Active (I
CC
)
L
H
H
H
L
High Z
Output Disabled
Active (I
CC
)
L
H
H
L
H
High Z
Output Disabled
Active (I
CC
)
L
L
X
L
L
Data In (I/O
O
I/O
15
)
Write
Active (I
CC
)
L
L
X
H
L
Data In (I/O
O
I/O
7
);
I/O
8
I/O
15
in High Z
Write
Active (I
CC
)
L
L
X
L
H
Data In (I/O
8
I/O
15
);
I/O
0
I/O
7
in High Z
Write
Active (I
CC
)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
45
CY62126DV30LL-45BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
CY62126DV30LL-45BVXI
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-free)
CY62126DV30LL-45ZSXI
ZS44
44-Lead TSOP Type II (Pb-free)
55
CY62126DV30L-55BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
CY62126DV30LL-55BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30L-55ZSI
ZS44
44-Lead TSOP Type II
CY62126DV30LL-55ZSI
ZS44
44-Lead TSOP Type II
CY62126DV30LL-55ZSXI
44-Lead TSOP Type II (Pb-Free)
70
CY62126DV30L-70BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
CY62126DV30LL-70BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30L-70ZSI
ZS44
44-Lead TSOP Type II
CY62126DV30LL-70ZSI
ZS44
44-Lead TSOP Type II
CY62126DV30LL-70ZSXI
44-Lead TSOP Type II (Pb-Free)
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 10 of 11
Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
44-pin TSOP II ZS44
51-85087-*A
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 11 of 11
Document History Page
Document Title: CY62126DV30 MoBL
1- Mbit (64K x 16) Static RAM
Document Number: 38-05230
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
117689
08/27/02
JUI
New Data Sheet
*A
127313
06/13/03
MPR
Changed From Advanced Status to Preliminary.
Changed I
SB2
to 5
A (L), 4 A (LL)
Changed I
CCDR
to 4
A (L), 3 A (LL)
Changed C
IN
from 6 pF to 8 pF
*B
128340
07/22/03
JUI
Changed from Preliminary to Final
Add 70-ns speed, updated ordering information
*C
129002
08/29/03
CDY
Changed I
CC
1 MHz typ from 0.5 mA to 0.85 mA
*D
238050
See ECN
AJU
Fixed typo: Changed t
DBE
from 70 ns to 35 ns
*E
316039
See ECN
PCI
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #8 on page #4
Added Pb-Free package ordering information on page # 9
Changed 44-pin TSOP-II package name from Z44 to ZS44
PDF 
ZIP