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256K (32K x 8) Static RAM
CY62256
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05248 Rev. *C
Revised June 25, 2004
Features
Temperature Ranges
-- Commercial: 0C to 70C
-- Industrial: 40C to 85C
-- Automotive: 40C to 125C
High speed: 55 ns and 70 ns
Voltage range: 4.5V5.5V operation
Low active power (70 ns, LL version, Com'l and Ind'l)
-- 275 mW (max.)
Low standby power (70 ns, LL version, Com'l and Ind'l)
-- 28
W (max.)
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 450-mil-wide (300-mil
body width) 28-lead narrow SOIC, 28-lead TSOP-1,
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP
packages
Functional Description
[1]
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
512 x 512
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
10
A
13
A
11
A
12
A
A
14
A
1
0
Logic Block Diagram
Note:
1.
For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
CY62256
Document #: 38-05248 Rev. *C
Page 2 of 12
Product Portfolio
Pin Configurations
Pin Definitions
Product
V
CC
Range (V)
Speed
(ns)
Power Dissipation
Operating, I
CC
(mA)
Standby, I
SB2
(
A)
Min.
Typ.
[2]
Max.
Typ.
[2]
Max.
Typ.
[2]
Max.
CY62256
Commercial
4.5
5.0
5.5
70
28
55
1
5
CY62256L
Com'l / Ind'l
55/70
25
50
2
50
CY62256LL
Commercial
70
25
50
0.1
5
CY62256LL
Industrial
55/70
25
50
0.1
10
CY62256LL
Automotive
55
25
50
0.1
15
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
Narrow SOIC
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
22
23
24
25
26
27
28
1
2
5
10
11
15
14
13
12
16
19
18
17
3
4
20
21
7
6
8
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
TSOP I
Top View
(not to scale)
Reverse Pinout
22
23
24
25
26
27
28
1
2
5
10
11
15
14
13
12
16
19
18
17
3
4
20
21
7
6
8
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
TSOP I
Top View
(not to scale)
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
Pin Number
Type
Description
1-10, 21, 23-26
Input
A
0
-A
14
. Address Inputs
11-13, 15-19,
Input/Output
I/O
0
-I/O
7
. Data lines. Used as input or output lines depending on operation
27
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20
Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
22
Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins
14
Ground
GND. Ground for the device
28
Power Supply Vcc. Power supply for the device
Notes:
2.
Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T
A
= 25
C, V
CC
). Parameters are guaranteed by design and characterization, and not 100% tested.
CY62256
Document #: 38-05248 Rev. *C
Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
C to +150C
Ambient Temperature with
Power Applied..............................................-55
C to +125C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[3]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
.................................0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient Temperature (T
A
)
[4]
V
CC
Commercial
0
C to +70
C 5V
10%
Industrial
40
C to +85
C 5V
10%
Automotive
40
C to +125
C 5V
10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
CY62256
-55
CY62256
-70
Unit
Min. Typ.
[2]
Max.
Min. Typ.
[2]
Max.
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-1.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+0.5V
2.2
V
CC
+0.5V
V
V
IL
Input LOW Voltage
0.5
0.8
0.5
0.8
V
I
IX
Input Leakage Current
GND < V
I
< V
CC
0.5
+0.5
0.5
+0.5
A
I
OZ
Output Leakage Current GND < V
O
< V
CC
, Output Disabled
0.5
+0.5
0.5
+0.5
A
I
CC
V
CC
Operating Supply
Current
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
28
55
28
55
mA
L
25
50
25
50
mA
LL
25
50
25
50
mA
I
SB1
Automatic CE
Power-down Current--
TTL Inputs
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
, f =
f
MAX
0.5
2
0.5
2
mA
L
0.4
0.6
0.4
0.6
mA
LL
0.3
0.5
0.3
0.5
mA
I
SB2
Automatic CE
Power-down Current--
CMOS Inputs
Max. V
CC
, CE > V
CC
- 0.3V
V
IN
> V
CC
- 0.3V, or V
IN
<
0.3V, f = 0
1
5
1
5
mA
L
2
50
2
50
A
LL
0.1
5
0.1
5
A
LL - Ind'l
0.1
10
0.1
10
A
LL -
Auto
0.1
15
A
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
6
pF
C
OUT
Output Capacitance
8
pF
Notes:
3.
V
IL
(min.)
=
-
2.0V for pulse durations of less than 20 ns.
4.
T
A
is the "Instant-On" case temperature.
5.
Tested initially and after any design or process changes that may affect these parameters.
CY62256
Document #: 38-05248 Rev. *C
Page 4 of 12
AC Test Loads and Waveforms
Data Retention Characteristics
Parameter
Description
Conditions
[6]
Min.
Typ.
[2]
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
L
V
CC
= 3.0V, CE > V
CC
- 0.3V,
V
IN
> V
CC
- 0.3V, or V
IN
< 0.3V
2
50
A
LL
0.1
5
A
LL - Ind'l
0.1
10
A
LL - Auto
0.1
10
A
t
CDR
[5]
Chip Deselect to Data Retention Time
0
ns
t
R
[5]
Operation Recovery Time
t
RC
ns
Data Retention Waveform
Notes:
6.
No input may exceed V
CC
+ 0.5V.
3.0V
5V
OUTPUT
R1 1800
R2
990
100 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
5V
OUTPUT
R1 1800
R2
990
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.77V
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
639
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
Thermal Resistance
Description
Test Conditions
Symbol
DIP
SOIC
TSOP
RTSOP
Unit
Thermal Resistance
(Junction to Ambient)
[5]
Still Air, soldered on a 4.25 x 1.125
inch, 4-layer printed circuit board
JA
75.61
76.56
93.89
93.89
C/W
Thermal Resistance
(Junction to Case)
[5]
JC
43.12
36.07
24.64
24.64
C/W
CY62256
Document #: 38-05248 Rev. *C
Page 5 of 12
Switching Characteristics
Over the Operating Range
[7]
Parameter
Description
CY62256
-55
CY62256
-70
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
ns
t
OHA
Data Hold from Address Change
5
5
ns
t
ACE
CE LOW to Data Valid
55
70
ns
t
DOE
OE LOW to Data Valid
25
35
ns
t
LZOE
OE LOW to Low-Z
[8]
5
5
ns
t
HZOE
OE HIGH to High-Z
[8, 9]
20
25
ns
t
LZCE
CE LOW to Low-Z
[8]
5
5
ns
t
HZCE
CE HIGH to High-Z
[8, 9]
20
25
ns
t
PU
CE LOW to Power-up
0
0
ns
t
PD
CE HIGH to Power-down
55
70
ns
Write Cycle
[10, 11]
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE LOW to Write End
45
60
ns
t
AW
Address Set-up to Write End
45
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-up to Write Start
0
0
ns
t
PWE
WE Pulse Width
40
50
ns
t
SD
Data Set-up to Write End
25
30
ns
t
HD
Data Hold from Write End
0
0
ns
t
HZWE
WE LOW to High-Z
[8, 9]
20
25
ns
t
LZWE
WE HIGH to Low-Z
[8]
5
5
ns
Switching Waveforms
Notes:
7.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
12. Device is continuously selected. OE, CE = V
IL
.
13. WE is HIGH for Read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1
[12, 13]
CY62256
Document #: 38-05248 Rev. *C
Page 6 of 12
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
IH
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
Read Cycle No. 2
[13, 14]
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE
Write Cycle No. 1 (WE Controlled)
[10, 15, 16]
17
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
CE
DATA
IN
VALID
Write Cycle No. 2 (CE Controlled)
[10, 15, 16]
CY62256
Document #: 38-05248 Rev. *C
Page 7 of 12
Switching Waveforms
(continued)
DATA I/O
ADDRESS
t
HD
t
SD
t
LZWE
t
SA
t
HA
t
AW
t
WC
CE
WE
t
HZWE
DATA
IN
VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
[11, 16]
NOTE 17
CY62256
Document #: 38-05248 Rev. *C
Page 8 of 12
Typical DC and AC Characteristics
1.2
1.4
1.0
0.6
0.4
0.2
4.0
4.5
5.0
5.5
6.0
1.6
1.4
1.2
1.0
0.8
-
55
25
125
-
55
25
125
1.2
1.0
0.8
NORMALIZED t
AA
120
100
80
60
40
20
0.0
1.0
2.0
3.0
4.0
OUT
P
U
T
SOURCE C
URRENT
(mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (
C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (
C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
1.4
1.1
1.0
0.9
4.0
4.5
5.0
5.5
6.0
NO
RM
A
L
I
Z
ED
t
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0
1.0
2.0
3.0
4.0
OUT
P
UT SINK C
URRENT
(mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED I
CC
NORMALIZ
E
D
I, I
CC
S
B
I
CC
I
CC
V
CC
=5.0V
V
CC
=5.0V
T
A
=25
C
V
CC
=5.0V
T
A
=25
C
I
SB
T
A
=25
C
0.6
0.8
0
AA
1.3
1.2
V
IN
=5.0V
T
A
=25
C
1.4
V
CC
=5.0V
V
IN
=5.0V
-
55
25
105
2.5
2.0
1.5
CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (
C)
1.0
0.5
0.0
-0.5
I
SB
3.0
STANDBY
V
CC
=5.0V
V
IN
=5.0V
I
SB
2
A
CY62256
Document #: 38-05248 Rev. *C
Page 9 of 12
Typical DC and AC Characteristics
(continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
2.0
3.0
4.0
NORMALIZ
ED
I
PO
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
30.0
25.0
20.0
15.0
10.0
5.0
0
200
400
600
800
D
E
LT
A t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
1.25
1.00
0.75
10
20
30
40
NO
RMALIZED I
CC
CYCLE FREQUENCY (MHz)
NORMALIZED I
CC
vs.CYCLE TIME
0.0
5.0
0.0
1000
0.50
V
CC
=4.5V
T
A
=25
C
V
CC
=5.0V
T
A
=25
C
V
IN
=0.5V
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High-Z
Deselect/Power-down
Standby (I
SB
)
L
H
L
Data Out
Read
Active (I
CC
)
L
L
X
Data In
Write
Active (I
CC
)
L
H
H
High-Z
Output Disabled
Active (I
CC
)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
55
CY62256LL
-55SNI
SN28
28-lead (300-Mil Narrow Body) Narrow SOIC
Industrial
CY62256LL
-55ZI
Z28
28-lead Thin Small Outline Package
CY62256LL
-55SNE
SN28
28-lead (300-Mil Narrow Body) Narrow SOIC
Automotive
CY62256LL
-55ZE
Z28
28-lead Thin Small Outline Package
CY62256LL
-55ZRE
ZR28
28-lead Reverse Thin Small Outline Package
70
CY62256
-70SNC
SN28
28-lead (300-Mil Narrow Body) Narrow SOIC
Commercial
CY62256L
-70SNC
CY62256LL
-70SNC
CY62256L70SNI
Industrial
CY62256LL
-70SNI
CY62256LL
-70ZC
Z28
28-lead Thin Small Outline Package
Commercial
CY62256LL
-70ZI
Z28
Industrial
CY62256
-70PC
P15
28-lead (600-Mil) Molded DIP
Commercial
CY62256L
-70PC
P15
CY62256LL
-70PC
P15
CY62256LL
-70ZRI
ZR28
28-lead Reverse Thin Small Outline Package
Industrial
CY62256
Document #: 38-05248 Rev. *C
Page 10 of 12
Package Diagrams
51-85017-A
28-lead (600-mil) Molded DIP P15
51-85092-*B
28-lead (300-mil) SNC (Narrow Body) SN28
CY62256
Document #: 38-05248 Rev. *C
Page 11 of 12
Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams
(continued)
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28
51-85071-*G
51-85074-*F
28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28
CY62256
Document #: 38-05248 Rev. *C
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Document Title: CY62256 256K (32K x 8) Static RAM
Document Number: 38-05248
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
113454
03/06/02
MGN
Change from Spec number: 38-00455 to 38-05248
Remove obsolete parts from ordering info, standardize format
*A
115227
05/23/02
GBI
Changed SN Package Diagram
*B
116506
09/04/02
GBI
Added footnote 1.
Corrected package description in Ordering Information table
*C
238448
See ECN
AJU
Added Automotive product information
PDF 
ZIP