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Электронный компонент: CY7C006AV

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3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-06051 Rev. *A
Revised December 27, 2002
25/0251
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
0.35-micron CMOS for optimum speed/power
High-speed access: 20/25 ns
Low operating power
-- Active: I
CC
= 115 mA (typical)
-- Standby: I
SB3
= 10
A (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Pin select for Master or Slave
Commercial and Industrial Temperature Ranges
Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
Pin-compatible and functionally equivalent to
IDT70V05, 70V06, and 70V07.
Notes:
1.
I/O
0
I/O
7
for x8 devices; I/O
0
I/O
8
for x9 devices.
2.
A
0
A
11
for 4K devices; A
0
A
12
for 8K devices; A
0
A
13
for 16K devices; A
0
A
14
for 32K devices;
3.
BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A
0L
A
1114L
CE
L
OE
L
R/W
L
BUSY
L
I/O
Control
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
A
0L
A
1114L
True Dual-Ported
RAM Array
A
0R
A
1114R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
Address
Decode
A
0R
A
1114R
[1]
[1]
[3]
[3]
R/W
L
OE
L
I/O
0L
I/O
7/8L
CE
L
R/W
R
OE
R
I/O
0R
I/O
7/8R
CE
R
1215
8/9
1215
8/9
1215
1215
[2]
[2]
[2]
[2]
Logic Block Diagram
For the most recent information, visit the Cypress web site at www.cypress.com
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 2 of 20
Functional Description
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and
32K x8/9 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are pro-
vided, permitting independent, asynchronous access for reads
and writes to any location in memory. The devices can be uti-
lized as standalone 8/9-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16/18-bit or
wider master/slave dual-port static RAM. An M/S pin is provid-
ed for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
cessor/multiprocessor designs, communications status buffer-
ing, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Select (CE) pin.
Pin Configurations
Notes:
4.
I/O
8L
on the CY7C139AV.
5.
I/O
8R
on the CY7C139AV.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
Top View
68-Pin PLCC
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 33 34 35 36 37 38 39 40 41 42 43
5 4 3 2 1 68
66 65 64 63 62 61
A
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
A
2728 29 30
9 8 7 6
47
46
45
44
A
1R
A
2R
A
3R
A
4R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
25
26
6L
7L
A
8L
A
9L
A
A
10L
11L
V
CC
NC
NC
CE
L
SEM
L
R/W
L
OE
L
NC
I/O
I/O
1L
0L
A
A
6R
7R
A
8R
A
9R
A
10
R
NC
NC
CE
R
SE
M
R
R/W
R
OE
R
I/O
7R
GND
A
11
R
A
5R
A
5L
NC
CY7C138AV (4K x 8)
[5
]
[4
]
NC
NC
CY7C139AV (4K x 9)
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 3 of 20
Notes:
6.
I/O
8L
on the CY7C145AV.
7.
I/O
8R
on the CY7C145AV.
Pin Configurations
(continued)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
Top View
68-Pin PLCC
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 33 34 35 36 37 38 39 40 41 42 43
5 4 3 2 1 68
66 65 64 63 62 61
A
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
A
2728 29 30
9 8 7 6
47
46
45
44
A
1R
A
2R
A
3R
A
4R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
25
26
6L
7L
A
8L
A
9L
A
A
10
L
11
L
V
CC
NC
NC
CE
L
SE
M
L
R/W
L
OE
L
NC
I/
O
I/
O
1L
0L
A
A
6R
7R
A
8R
A
9R
A
10R
NC
NC
CE
R
SEM
R
R/
W
R
OE
R
I/
O
7R
GND
A
11R
A
5R
A
5L
NC
A
12
L
A
12R
CY7C144AV (8K x 8)
[7]
[6]
CY7C145AV (8K x 9)
64-Pin TQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
16
GND
OE
R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
GND
V
CC
A
4L
A
3L
A
2L
A
1L
A
0L
GND
BUSY
L
BUSY
R
M/S
A
0R
A
1R
A
2R
A
3R
A
4R
INT
L
INT
R
I/O
7R
A
5R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
NC
CE
R
SEM
R
R/W
R
V
CC
OE
L
I/O
1L
I/O
0L
A
5L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
NC
CE
L
SEM
L
R/W
L
CY7C144AV (8K x 8)
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 4 of 20
Notes:
8.
I/O for CY7C016AV and CY7C017AV only. NC for other parts.
9.
Address line for CY7C007AV and CY7C017AV only. NC for other parts.
Pin Configurations
(continued)
Top View
68-Pin PLCC
V
CC
OE
L
I/O
1L
I/O
0L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
13L
CE
L
SEM
L
R/W
L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
GND
V
CC
A
4L
A
3L
A
2L
A
1L
A
0L
GND
BUSY
L
BUSY
R
M/S
A
0R
A
1R
A
2R
A
3R
A
4R
INT
L
INT
R
GND
OE
R
I/O
7R
A
5R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
13R
CE
R
SEM
R
R/W
R
A
5L
I/
O
8L
I/O6
R
CY7C006AV (16K x 8)
24
25
26
10
11
12
13
14
15
48
47
46
45
44
40
41
27
42
28
43
29
30
31
32
33
68
34
67
35
66
36
65
37
64
38
63
39
62
61
16
59
58
57
56
55
54
53
52
51
50
49
60
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
[8]
A
14R
[9]
A
14
L
[9]
CY7C007AV (32K x 8)
CY7C016AV (16K x 9)
CY7C017AV (32K x 9)
I/O
8R
[8]
64-Pin TQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
16
GND
OE
R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
GND
V
CC
A
4L
A
3L
A
2L
A
1L
A
0L
GND
BUSY
L
BUSY
R
M/S
A
0R
A
1R
A
2R
A
3R
A
4R
INT
L
INT
R
I/O
7R
A
5R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
13R
CE
R
SE
M
R
R/W
R
V
CC
OE
L
I/O
1L
I/O
0L
A
5L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
13L
CE
L
SE
M
L
R/W
L
CY7C006AV (16K x 8)
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 5 of 20
Maximum Ratings
[10]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
C to +150
C
Ambient Temperature with
Power Applied.............................................55
C to +125
C
Supply Voltage to Ground Potential ............... 0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................0.5V to V
CC
+0.5V
DC Input Voltage
[11]
.................................0.5V to V
CC
+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current .................................................... >200 mA
Notes:
10. The Voltage on any input or I/O pin can not exceed the power pin during power-up.
11. Pulse width < 20 ns.
12. Industrial parts are available in CY7C007AV and CY7C017AV only.
Selection Guide
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-25
Maximum Access Time (ns)
20
25
Typical Operating Current (mA)
120
115
Typical Standby Current for I
SB1
(mA)
(Both Ports TTL level)
35
30
Typical Standby Current for I
SB3
(
A)
(Both Ports CMOS level)
10
A
10
A
Pin Definitions
Left Port
Right Port
Description
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
A
14L
A
0R
A
14R
Address (A
0
A
11
for 4K devices; A
0
A
12
for 8K devices; A
0
A
13
for 16K devices; A
0
A
14
for 32K)
I/O
0L
I/O
8L
I/O
0R
I/O
8R
Data Bus Input/Output (I/O
0
I/O
7
for x8 devices and I/O
0
I/O
8
for x9)
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
CC
Power
GND
Ground
NC
No Connect
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
3.3V
300 mV
Industrial
[12]
40
C to +85
C 3.3V
300 mV