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PRELIMINARY
512K x 8 Static RAM
CY7C1049
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05063 Rev. **
Revised August 31, 2001
049
Features
High speed
-- t
AA
= 15 ns
Low active power
-- 1210 mW (max.)
Low CMOS standby power (Commercial L version)
-- 2.75 mW (max.)
2.0V Data Retention (400
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1049 is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. Writing to the de-
vice is accomplished by taking chip enable (CE) and write en-
able (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
18
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
14
15
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODE
R
SENS
E AM
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
CE
A
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14
23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15
21
22
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
5
I/O
4
10491
A
9
A
0
I/O
0
I/O
1
I/O
2
OE
A
17
A
16
A
13
CE
10492
A
9
A
18
18
17
19
20
GND
I/O
7
I/O3
I/O
6
V
CC
A
10
A
11
NC
NC
A
10
Selection Guide
7C1049-12
7C1049-15
7C1049-17
7C1049-20
7C1049-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA)
240
220
195
185
180
Maximum CMOS Standby
Current (mA)
Com'l
8
8
8
8
8
Com'l
L
0.5
0.5
0.5
0.5
0.5
Ind'l
9
9
9
9
9
Military
10
10
Shaded areas contain advance information.
CY7C1049
PRELIMINARY
Document #: 38-05063 Rev. **
Page 2 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
4.5V5.5V
Industrial
40
C to +85
C
Military
55
C to +125
C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
7C1049-12
7C1049-15
7C1049-17
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
0.3
0.3
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
OUT
< V
CC
,
Output Disabled
1
+1
1
+1
1
+1
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
240
220
195
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
40
40
40
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f=0
Com'l
8
8
8
mA
Com'l
L
0.5
0.5
0.5
mA
Ind'l
9
9
9
mA
Military
10
10
10
mA
Shaded areas contain advance information.
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the "instant on" case temperature.
CY7C1049
PRELIMINARY
Document #: 38-05063 Rev. **
Page 3 of 10
Electrical Characteristics
Over the Operating Range (continued)
Test Conditions
7C1049-20
7C1049-25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
2.2
V
CC
+
0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
OUT
< V
CC
,
Output Disabled
1
+1
1
+1
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
185
180
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
40
40
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f=0
Com'l
8
8
mA
Com'l
L
0.5
0.5
mA
Ind'l
9
9
mA
Military
10
10
mA
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
8
pF
C
OUT
I/O Capacitance
8
pF
Note:
3.
Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
10493
10494
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
3ns
3 ns
OUTPUT
R1 481
R1 481
R2
255
R2
255
167
Equivalent to:
VENIN EQUIVALENT
1.73V
TH
CY7C1049
PRELIMINARY
Document #: 38-05063 Rev. **
Page 4 of 10
Switching Characteristics
[4]
Over the Operating Range
7C1049-12
7C1049-15
7C1049-17
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
12
15
17
ns
t
AA
Address to Data Valid
12
15
17
ns
t
OHA
Data Hold from Address Change
3
3
3
ns
t
ACE
CE LOW to Data Valid
12
15
17
ns
t
DOE
OE LOW to Data Valid
6
7
8
ns
t
LZOE
OE LOW to Low Z
[6]
0
0
0
ns
t
HZOE
OE HIGH to High Z
[5, 6]
6
7
7
ns
t
LZCE
CE LOW to Low Z
[6]
3
3
3
ns
t
HZCE
CE HIGH to High Z
[5, 6]
6
7
7
ns
t
PU
CE LOW to Power-Up
0
0
0
ns
t
PD
CE HIGH to Power-Down
12
15
17
ns
WRITE CYCLE
[7,8]
t
WC
Write Cycle Time
12
15
17
ns
t
SCE
CE LOW to Write End
10
12
12
ns
t
AW
Address Set-Up to Write End
10
12
12
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
10
12
12
ns
t
SD
Data Set-Up to Write End
7
8
8
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[6]
3
3
3
ns
t
HZWE
WE LOW to High Z
[5, 6]
6
7
8
ns
Shaded areas contain advance information.
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
6.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
CY7C1049
PRELIMINARY
Document #: 38-05063 Rev. **
Page 5 of 10
Switching Characteristics
[4]
Over the Operating Range (continued)
Parameter
Description
7C1049-20
7C1049-25
Unit
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
20
25
ns
t
AA
Address to Data Valid
20
25
ns
t
OHA
Data Hold from Address Change
3
5
ns
t
ACE
CE LOW to Data Valid
20
25
ns
t
DOE
OE LOW to Data Valid
8
10
ns
t
LZOE
OE LOW to Low Z
[6]
0
0
ns
t
HZOE
OE HIGH to High Z
[5, 6]
8
10
ns
t
LZCE
CE LOW to Low Z
[6]
3
5
ns
t
HZCE
CE HIGH to High Z
[5, 6]
8
10
ns
t
PU
CE LOW to Power-Up
0
0
ns
t
PD
CE HIGH to Power-Down
20
25
ns
WRITE CYCLE
[7]
t
WC
Write Cycle Time
20
25
ns
t
SCE
CE LOW to Write End
13
15
ns
t
AW
Address Set-Up to Write End
13
15
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
13
15
ns
t
SD
Data Set-Up to Write End
9
10
ns
t
HD
Data Hold from Write End
0
0
ns
t
LZWE
WE HIGH to Low Z
[6]
3
5
ns
t
HZWE
WE LOW to High Z
[5, 6]
8
10
ns
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
[10]
Min.
Max
Unit
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
Com'l
L V
CC
= V
DR
= 3.0V,
CE > V
CC
0.3V
V
IN
> V
CC
0.3V or V
IN
< 0.3V
200
A
Ind'l
1
mA
Military
2
mA
t
CDR
[3]
Chip Deselect to Data Retention Time
0
ns
t
R
[9]
Operation Recovery Time
t
RC
ns
Notes:
9.
t
r
< 3 ns for the -12 and -15 speeds. t
r
< 5 ns for the -20 ns and slower speeds.
10. No input may exceed V
CC
+ 0.5V.
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