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512K x 8 Static RAM
CY7C1049BV33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05139 Rev. *A
Revised September 13, 2002
049BV33
Features
High speed
-- t
AA
= 15 ns
Low active power
-- 504 mW (max.)
Low CMOS standby power (Commercial L version)
-- 1.8 mW (max.)
2.0V Data Retention (660
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
[1]
The CY7C1049BV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writ-
ing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O
0
through I/O
7
) is then written into the location specified on
the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
14
15
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
RO
W
D
E
CO
D
E
R
SE
N
S
E A
M
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
CE
A
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14
23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15
21
22
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
5
I/O
4
A
9
A
0
I/O
0
I/O
1
I/O
2
OE
A
17
A
16
A
13
CE
A
9
A
18
18
17
19
20
GND
I/O
7
I/O3
I/O
6
V
CC
A
10
A
11
NC
NC
A
10
Top View
TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
V
CC
A
5
A
6
A
7
A
8
A
0
A
1
V
SS
A
17
A
2
CE
I/O
0
A
3
A
4
18
17
20
19
I/O
1
27
28
25
26
22
21
23
24
V
SS
I/O
2
I/O
3
A
16
A
15
V
CC
OE
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
9
A
10
NC
NC
NC
NC
NC
NC
NC
A
18
NC
NC
NC
Selection Guide
-12
-15
-17
-20
-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA) Comm'l
200
180
170
160
150
Ind'l
220
200
180
170
170
Maximum CMOS Standby
Current (mA)
Com'l/Ind'l
8
8
8
8
8
Com'l
L
0.5
0.5
0.5
0.5
0.5
Note:
1.
For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
CY7C1049BV33
Document #: 38-05139 Rev. *A
Page 2 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[2]
.....0.5V to +4.6V
DC Voltage Applied to Outputs
[2]
in High Z State .......................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
................................ 0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
3.3V
0.3V
Industrial
40
C to +85
C
DC Electrical Characteristics
Over the Operating Range
Parame-
ter
Description
Test Conditions
-12
-15
-17
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
2.2
V
CC
+ 0.5
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
[2]
0.5
0.8
0.5
0.8
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
OUT
< V
CC
,
Output Disabled
1
+1
1
+1
1
+1
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Comm'l
200
180
170
mA
Ind'l
220
200
180
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
30
30
30
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f = 0
Com'l/Ind'l
8
8
8
mA
Com'l
L
0.5
0.5
0.5
mA
Note:
2.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
CY7C1049BV33
Document #: 38-05139 Rev. *A
Page 3 of 10
DC Electrical Characteristics
Over the Operating Range (continued)
-20
-25
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
[2]
0.5
0.8
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
OUT
< V
CC
,
Output Disabled
1
+1
1
+1
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Com'l
160
150
mA
Ind'l
170
170
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
30
30
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f = 0
Com'l/Ind'l
8
8
mA
Com'l
L
0.5
0.5
mA
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 3.3V
8
pF
C
OUT
I/O Capacitance
8
pF
AC Test Loads and Waveforms
Note:
3.
Tested initially and after any design or process changes that may affect these parameters.
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
OUTPUT
(a)
(b)
R1 317
167
R2
351
VENIN EQUIVALENT
TH
1.73V
RiseTime:1 V/ns
Fall time:
1 V/ns
CY7C1049BV33
Document #: 38-05139 Rev. *A
Page 4 of 10
AC Switching Characteristics
[4]
Over the Operating Range
-12
-15
-17
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
power
V
CC
(typical) to the First Access
[5]
1
1
1
s
t
RC
Read Cycle Time
12
15
17
ns
t
AA
Address to Data Valid
12
15
17
ns
t
OHA
Data Hold from Address Change
3
3
3
ns
t
ACE
CE LOW to Data Valid
12
15
17
ns
t
DOE
OE LOW to Data Valid
6
7
8
ns
t
LZOE
OE LOW to Low Z
0
0
0
ns
t
HZOE
OE HIGH to High Z
[6, 7]
6
7
8
ns
t
LZCE
CE LOW to Low Z
[7]
3
3
3
ns
t
HZCE
CE HIGH to High Z
[6, 7]
6
7
8
ns
t
PU
CE LOW to Power-Up
0
0
0
ns
t
PD
CE HIGH to Power-Down
12
15
17
ns
Write Cycle
[8, 9]
t
WC
Write Cycle Time
12
15
17
ns
t
SCE
CE LOW to Write End
10
12
13
ns
t
AW
Address Set-Up to Write End
10
12
13
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
10
12
13
ns
t
SD
Data Set-Up to Write End
7
8
9
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
3
3
ns
t
HZWE
WE LOW to High Z
[6, 7]
6
7
8
ns
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5.
This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.
power
time has to be provided initially before a read/write operation
is started.
6.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
CY7C1049BV33
Document #: 38-05139 Rev. *A
Page 5 of 10
AC Switching Characteristics
[4]
Over the Operating Range (continued)
Parameter
Description
-20
-25
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
power
V
CC
(typical) to the First Access
[6]
1
1
s
t
RC
Read Cycle Time
20
25
ns
t
AA
Address to Data Valid
20
25
ns
t
OHA
Data Hold from Address Change
3
3
ns
t
ACE
CE LOW to Data Valid
20
25
ns
t
DOE
OE LOW to Data Valid
8
10
ns
t
LZOE
OE LOW to Low Z
0
0
ns
t
HZOE
OE HIGH to High Z
[6, 7]
8
10
ns
t
LZCE
CE LOW to Low Z
[7]
3
3
ns
t
HZCE
CE HIGH to High Z
[6, 7]
8
10
ns
t
PU
CE LOW to Power-Up
0
0
ns
t
PD
CE HIGH to Power-Down
20
25
ns
Write Cycle
[9]
t
WC
Write Cycle Time
20
25
ns
t
SCE
CE LOW to Write End
13
15
ns
t
AW
Address Set-Up to Write End
13
15
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
13
15
ns
t
SD
Data Set-Up to Write End
9
10
ns
t
HD
Data Hold from Write End
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
3
ns
t
HZWE
WE LOW to High Z
[6, 7]
8
10
ns
Data Retention Characteristics
Over the Operating Range (For L version only)
Parameter
Description
Conditions
[10]
Min.
Max
Unit
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
V
CC
= V
DR
= 2.0V,
CE > V
CC
0.3V
V
IN
> V
CC
0.3V or V
IN
< 0.3V
330
A
t
CDR
[3]
Chip Deselect to Data Retention
Time
0
ns
t
R
[11]
Operation Recovery Time
t
RC
ns
Notes:
10. No input may exceed V
CC
+ 0.5V
11.
.t
r
< 3 ns for the -12 and -15 speeds. t
r
< 5 ns for the -20 ns and slower speeds.
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