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2K x 8 Static RAM
CY7C128A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05028 Rev. **
Revised August 24, 2001
28A
Features
Automatic power-down when deselected
CMOS for optimum speed/power
High speed
-- 15 ns
Low active power
-- 660 mW (commercial)
-- 688 mW (military--20 ns)
Low standby power
-- 110 mW (20 ns)
TTL-compatible inputs and outputs
Capable of withstanding greater than 2001V electro-
static discharge
V
IH
of 2.2V
Functional Description
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), and active LOW
Output Enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O
0
through I/O
7
) is written into the
memory location specified on the address pins (A
0
through
A
10
).
Reading the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while Write Enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear on
the eight I/O pins.
The I/O pins remain in high-impedance state when Chip En-
able (CE) or Output Enable (OE) is HIGH or Write Enable (WE)
is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
C128A1
A
1
A
2
A
4
A
5
A
6
COLUMN
DECODER
ROW DECODE
R
SE
NSE A
M
P
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
Top View
LCC
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ/SOIC
12
13
A
6
A
5
A
4
A
3
WE
V
CC
A
8
A
9
A
10
I/O
5
I/O
4
I/O
3
C128A2
A
7
I/O
0
I/O
1
CE
OE
128 x 16 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
7C128A
A
0
C128A3
A
3
A
7
A
8
A
9
A
10
24
4
5
6
7
8
9
10
3 2 1
23
11 12 13 14 15
22
21
20
19
18
17
16
A
5
V
CC
7C128A
A
6
2
I/O
A
4
A
3
A
2
A
1
WE
CE
A
0
A
9
I/O
2
GND
I/O
7
I/O
6
A
2
A
1
A
0
3
I/O
4
I/O
5
I/O
GND
A
7
A
8
OE
A
10
I/O
7
I/O
6
I/O
0
I/O
1
Selection Guide
7C128A-15
7C128A-20
7C128A-25
7C128A-35
7C128A-45
Maximum Access Time (ns)
15
20
25
35
45
Maximum Operating
Current (mA)
Commercial
120
120
120
120
120
Military
-
125
125
125
125
Maximum Standby
Current (mA)
Commercial
40
20
20
20
20
Military
-
20
20
20
20
CY7C128A
Document #: 38-05028 Rev. **
Page 2 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 3.0V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
5V
10%
Military
[1]
55
C to +125
C
5V
10%
Electrical Characteristics
Over the Operating Range
[2]
7C128A-15
7C128A-20
7C128A-25
7C128A-35,45
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH
Voltage
V
CC
= Min.,
I
OH =
4.0 mA
2.4
2.4
2.4
2.4
V
V
OL
Output LOW
Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
0.4
V
V
IH
Input HIGH
Voltage
2.2
V
CC
2.2
V
CC
2.2
V
CC
2.2
V
CC
V
V
IL
Input LOW
Voltage
[3]
0.5
0.8
0.5
0.8
0.5
0.8
0.5
0.8
V
I
IX
Input Load
Current
GND < V
I
< V
CC
10
+10
10
+10
10
+10
10
+10
A
I
OZ
Output Leakage
Current
GND < V
I
< V
CC
Output Disabled
10
+10
10
+10
10
+10
10
+10
A
I
OS
Output Short
CircuitCurrent
[4]
V
CC
= Max.,
V
OUT
= GND
300
300
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.
I
OUT
= 0 mA
Com'l
120
120
120
120
mA
Mil
-
125
125
125
I
SB1
Automatic CE
Power-Down
Current
Max. V
CC
,
CE > V
IH,
Min. Duty Cycle
= 100%
Com'l
40
40
20
20
mA
Mil
-
40
40
20
I
SB2
Automatic CE
Power-Down
Current
Max. V
CC
,
CE
1
>V
CC
0.3V,
V
IN
> V
CC
0.3V
or V
IN
< 0.3V
Com'l
40
20
20
20
mA
Mil
-
20
20
20
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
10
pF
C
OUT
Output Capacitance
10
pF
Notes:
1.
T
A
is the "instant on" case temperature.
2.
See the last page of this specification for Group A subgroup testing information.
3.
V
IL
(min.) = 3.0V for pulse durations less than 30 ns.
4.
Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5.
Tested initially and after any design or process changes that may affect these parameters.
CY7C128A
Document #: 38-05028 Rev. **
Page 3 of 10
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
5 ns
5 ns
5V
OUTPUT
C128A4
R1 481
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
C128A5
(a)
(b)
OUTPUT
1.73V
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
167
Switching Characteristics
Over the Operating Range
[2, 6]
7C128A-15
7C128A-20
7C128A-25
7C128A-35
7C128A-45
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
20
25
35
45
ns
t
AA
Address to Data Valid
15
20
25
35
45
ns
t
OHA
Data Hold from Address Change
5
5
5
5
5
ns
t
ACE
CE LOW to Data Valid
15
20
25
35
45
ns
t
DOE
OE LOW to Data Valid
10
10
12
15
20
ns
t
LZOE
OE LOW to Low Z
3
3
3
3
3
ns
t
HZOE
OE HIGH to High Z
[7]
8
8
10
12
15
ns
t
LZCE
CE LOW to Low Z
[8]
5
5
5
5
5
ns
t
HZCE
CE HIGH to High Z
[7, 8]
8
8
10
15
15
ns
t
PU
CE LOW to Power-Up
0
0
0
0
0
ns
t
PD
CE HIGH to Power-Down
15
20
20
20
25
ns
WRITE CYCLE
[9]
t
WC
Write Cycle Time
15
20
20
25
40
ns
t
SCE
CE LOW to Write End
12
15
20
25
30
ns
t
AW
Address Set-Up to Write End
12
15
20
25
30
ns
t
HA
Address Hold from Write End
0
0
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
0
0
ns
t
PWE
WE Pulse Width
12
15
15
20
20
ns
t
SD
Data Set-Up to Write End
10
10
10
15
15
ns
t
HD
Data Hold from Write End
0
0
0
0
0
ns
t
HZWE
WE LOW to High Z
[7]
7
7
7
10
15
ns
t
LZWE
WE HIGH to Low Z
5
5
5
5
5
ns
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady state voltage.
8.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C128A
Document #: 38-05028 Rev. **
Page 4 of 10
Switching Waveforms
Read Cycle No. 1
[10, 11]
Read Cycle No. 2
[10, 12]
Write Cycle No. 1 (WE Controlled)
[9, ]
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected. OE, CE = V
IL
.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.
ADDRESS
C128A6
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
C128A7
V
CC
SUPPLY
CURRENT
t
WC
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
HZWE
t
LZWE
t
SD
C128A8
CE
WE
DATA IN
DATA I/O
ADDRESS
DATA
IN
VALID
CY7C128A
Document #: 38-05028 Rev. **
Page 5 of 10
Write Cycle No. 2 (CE Controlled)
[9, 13, 14]
Notes:
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
t
WC
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
HZWE
t
SD
ADDRESS
CE
WE
DATA IN
DATA I/O
C128A9
DATA
IN
VALID
Typical DC and AC Characteristics
1.2
1.4
1.0
0.6
0.4
0.2
4.0
4.5
5.0
5.5
6.0
1.6
1.4
1.2
1.0
0.8
55
25
125
55
25
125
1.2
1.0
0.8
NO
RM
A
L
I
Z
E
D
t
AA
120
100
80
60
40
20
0.0
1.0
2.0
3.0
4.0
OUT
P
UT
S
O
U
RCE
CURRE
NT
(m
A
)
SUPPLY VOLTAGE(V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE(
C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE(
C)
OUTPUT VOLTAGE(V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
1.4
1.3
1.2
1.1
1.0
0.9
4.0
4.5
5.0
5.5
6.0
NO
R
M
A
L
I
Z
E
D
t
AA
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0
1.0
2.0
3.0
4.0
O
U
TP
UT
S
I
NK
CURRE
NT
(m
A
)
0
80
OUTPUT VOLTAGE(V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMA
L
I
Z
E
D
I
CC
, I
SB
NORMA
L
I
Z
E
D
I
CC
, I
SB
I
SB
V
CC
= 5.0V
V
IN
= 5.0V
I
CC
I
CC
V
CC
= 5.0V
V
CC
=5.0V
T
A
= 25
C
V
CC
=5.0V
T
A
= 2 5
C)
I
SB
T
A
= 25
C
0.6
0.8
0
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