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18-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05499 Rev. *B
Revised January 29, 2005
Features
18-Mb density (2M x 8, 1M x 18, 512K x 36)
250-MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
Two input clocks (K and K) for precise DDR timing
-- SRAM uses rising edges only
Two output clocks (C and C) account for clock skew
and flight time mismatching
Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4VV
DD
)
13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1316AV18 2M x 8
CY7C1318AV18 1M x 18
CY7C1320AV18 512K x 36
Functional Description
The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are
1.8V Synchronous Pipelined SRAM equipped with DDR-II
architecture. The DDR-II consists of an SRAM core with
advanced synchronous peripheral circuitry and a 1-bit burst
counter. Addresses for Read and Write are latched on
alternate rising edges of the input (K) clock. Write data is regis-
tered on the rising edges of both K and K. Read data is driven
on the rising edges of C and C if provided, or on the rising edge
of K and K if C/C are not provided. Each address location is
associated with two 8-bit words in the case of CY7C1316AV18
that burst sequentially into or out of the device. The burst
counter always starts with a "0" internally in the case of
CY7C1316AV18. On CY7C1318AV18 and CY7C1320AV18,
the burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1318AV18 and two 36-bit words in the case of
CY7C1320AV18 sequentially into or out of the device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) enable maximum system clocking
and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1316AV18)
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Re
ad Add. Decode
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
BWS
[1:0]
V
REF
W
r
ite Add. Decode
8
C
C
8
LD
Control
20
1M
x
8
A
r
r
a
y
1M x
8 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 2 of 20
1M x 18 Array
Write
Reg
Write
Reg
Logic Block Diagram (CY7C1318AV18)
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. D
e
cod
e
Read Data Reg.
R/W
DQ
[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS
[1:0]
V
REF
W
r
ite Add. D
e
co
de
18
20
C
C
18
LD
Control
Burst
Logic
A0
A
(19:1)
19
CQ
CQ
R/W
DOFF
Logic Block Diagram (CY7C1320AV18)
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add
.
Decode
Read Data Reg.
R/W
DQ
[35:0]
Output
Logic
Reg.
Reg.
Reg.
72
36
144
36
BWS
[3:0]
V
REF
W
r
ite Add
.
Decode
72
19
C
C
36
LD
Control
Burst
Logic
A0
A
(18:1)
18
512K x 36 Array
Write
Reg
Write
Reg
CQ
CQ
36
R/W
DOFF
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
800
750
700
mA
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 3 of 20
Pin Configurations
CY7C1316AV18 (2M 8)--11 15 FBGA
2
3
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
V
SS
/72M
A
BWS
1
K
R/W
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
TCK
NC
NC
A NC
K
BWS
0
V
SS
A
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
DQ4
NC
V
DDQ
NC
NC
NC
NC
DQ7
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
DQ5
V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
C
V
SS
A
A
A
NC
V
SS
NC
V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
NC
DQ6
NC
NC
NC
V
DD
A
8
9
10
11
NC
A
V
SS
/36M
LD
CQ
A NC
NC
DQ3
V
SS
NC
NC
NC
NC
V
SS
NC
DQ2
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC
NC
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
NC
DQ1
NC
V
DDQ
V
DDQ
NC
V
SS
NC
NC
NC
TDI
TMS
V
SS
A
NC
A
NC
NC
NC
ZQ
NC
DQ0
NC
NC
NC
NC
A
CY7C1318AV18 (1M 18)--11 15 FBGA
2
3
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
V
SS
/72M
A
BWS
1
K
R/W
NC
DQ9
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
TCK
NC
NC
A NC
K
BWS
0
V
SS
A
A0
A
DQ10
V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
DQ11
NC
V
DDQ
NC
DQ14
NC
DQ16
DQ17
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
DQ13
V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
C
V
SS
A
A
A
NC
V
SS
NC
V
SS
DQ12
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
NC
DQ15
NC
NC
NC
V
DD
A
8
9
10
11
DQ0
A
V
SS
/36M
LD
CQ
A NC
NC
DQ8
V
SS
NC
DQ7
NC
NC
V
SS
NC
DQ6
NC
NC
NC
V
REF
NC
DQ3
V
DDQ
NC
V
DDQ
NC
DQ5
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
NC
DQ4
NC
V
DDQ
V
DDQ
NC
V
SS
NC
NC
NC
TDI
TMS
V
SS
A
NC
A
NC
NC
NC
ZQ
NC
DQ2
NC
DQ1
NC
NC
A
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 4 of 20
Pin Definitions
Pin Name
I/O
Pin Description
DQ
[x:0]
Input/Output-
Synchronous
Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When read access is deselected, Q
[x:0]
are automatically three-stated.
CY7C1316AV18
-
DQ
[7:0]
CY7C1318AV18
-
DQ
[17:0]
CY7C1320AV18
-
DQ
[35:0]
LD
Input-
Synchronous
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data.
BWS
0
, BWS
1
,
BWS
2
, BWS
3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
-
active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1316AV18
-
BWS
0
controls D
[3:0]
and BWS
1
controls D
[7:4]
.
CY7C1318AV18
-
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1320AV18
-
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0
Input-
Synchronous
Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316AV18, a
single 1M x 18 array for CY7C1318AV18, and a single array of 512K x 36 for CY7C1320AV18.
CY7C1316AV18 Since the least significant bit of the address internally is a "0," only 20 external
address inputs are needed to access the entire memory array.
CY7C1318AV18 A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 20 address inputs are needed to access the entire memory array.
CY7C1320AV18 A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 19 address inputs are needed to access the entire memory array. All the address inputs
are ignored when the appropriate port is deselected.
Pin Configurations
(continued)
CY7C1320AV18 (512K 36)--11 15 FBGA
2
3
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
V
SS
/144M NC/36M
BWS
2
K
R/W
BWS
1
DQ27
DQ18
NC
NC
NC
TDO
NC
NC
DQ31
NC
NC
NC
TCK
NC
DQ28
A BWS
3
K
BWS
0
V
SS
A
A0
A
DQ19
V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
DQ20
DQ21
V
DDQ
DQ32
DQ23
DQ34
DQ25
DQ26
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
DQ22
V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
C
V
SS
A
A
A
DQ29
V
SS
NC
V
SS
DQ30
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
NC
DQ33
NC
DQ35
DQ24
V
DD
A
8
9
10
11
DQ0
A
V
SS
/72M
LD
CQ
A NC
NC
DQ8
V
SS
NC
DQ17
DQ7
NC
V
SS
NC
DQ6
DQ14
NC
NC
V
REF
NC
DQ3
V
DDQ
NC
V
DDQ
NC
DQ5
V
DDQ
V
DDQ
V
DDQ
DQ4
V
DDQ
NC
DQ13
NC
V
DDQ
V
DDQ
NC
V
SS
NC
DQ1
NC
TDI
TMS
V
SS
A
NC
A
DQ16
DQ15
NC
ZQ
DQ12
DQ2
DQ10
DQ11
DQ9
NC
A
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 5 of 20
R/W
Input-
Synchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
C
Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
C
Input-
Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
K
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous data being presented to the device
and to drive out data through Q
[x:0]
when in single clock mode.
CQ
Output-
Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
CQ
Output-
Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2
RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V
DD
,
which enables the minimum impedance mode. This pin cannot be connected directly to GND or
left unconnected.
DOFF
Input
DLL Turn Off--active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, "DLL Operation in the
QDRTM-II."
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level.
NC/72M
N/A
Address expansion for 72M. This is not connected to the die and so can be tied to any voltage
level.
V
SS
/72M
Input
Address expansion for 72M. This must be tied LOW.
V
SS
/144M
Input
Address expansion for 144M. This must be tied LOW.
V
SS
/288M
Input
Address expansion for 288M. This must be tied LOW.
V
REF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
V
DD
Power Supply Power supply inputs to the core of the device.
V
SS
Ground
Ground for the device.
V
DDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
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