128K x 32 Synchronous Pipelined Cache RAM

CY7C1339B

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05141 Rev. *A

Revised March 27, 2002

Features

· Supports 100-MHz bus for Pentium

and PowerPC

operations with zero wait states

· Fully registered inputs and outputs for pipelined

operation

· 128K × 32 common I/O architecture
· 3.3V core power supply
· 2.5V / 3.3V I/O operation
· Fast clock-to-output times

-- 3.5 ns (for 166-MHz device)

-- 4.0 ns (for 133-MHz device)

-- 5.5 ns (for 100-MHz device)

· User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences

· Separate processor and controller address strobes
· Synchronous self-timed writes
· Asynchronous output enable
· Offered in JEDEC-standard 100-pin TQFP and 119-ball

BGA packages

· "ZZ" Sleep Mode and Stop Clock options

Functional Description

The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.

The CY7C1339B I/O pins can operate at either the 2.5V or the
3.3V level; the I/O pins are 3.3V-tolerant when V

DDQ

= 2.5V.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 3.5 ns (166-MHz
device).

The CY7C1339B supports either the interleaved burst
sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the four Byte Write
Select (BW

[3:0]

) inputs. A Global Write Enable (GW) overrides

all Byte Write inputs and writes data to all four bytes. All Writes
are conducted with on-chip synchronous self-timed Write
circuitry.

Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a Read cycle when emerging from a deselected
state.

CLK

ADV

ADSC

[16:0]

BWE

BURST

COUNTER

DQ[31:24]

BYTEWRITE

REGISTERS

ADDRESS

OUTPUT

REGISTERS

INPUT

REGISTERS

128K × 32

MEMORY

ARRAY

CLK

CLR

SLEEP

CONTROL

DQ[23:16]

BYTEWRITE

REGISTERS

DQ[15:8]

BYTEWRITE

REGISTERS

DQ[7:0]

BYTEWRITE

REGISTERS

ENABLE

CLK

ENABLE DELAY

CLK

[1;0]

)

MODE

ADSP

Logic Block Diagram

[31:0]

CY7C1339B

Document #: 38-05141 Rev. *A

Page 2 of 17

Pin Configurations

Selection Guide

7C1339B-166

7C1339B-133

7C1339B-100

Unit

Maximum Access Time

3.5

4.0

5.5

Maximum Operating Current

420

375

325

Maximum CMOS Standby Current

DNU

NC
DQ

DDQ

SSQ

DDQ

NC
V

ZZ
DQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

CLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

BYTE0

BYTE1

BYTE3

BYTE2

100-pin TQFP

CY7C1339B

CY7C1339B

Document #: 38-05141 Rev. *A

Page 4 of 17

Pin Definitions

Pin Name

I/O

Pin Description

[16:0]

Input-

Synchronous

Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE

, CE

, and

are sampled active. A

[1:0]

feed the

two-bit counter.

[3:0]

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written, regardless of the values on BW

[3:0]

and BWE).

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE

to select/deselect the device. ADSP is ignored if CE

is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, Asynchronous Input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected
state.

ADV

Input-

Synchronous

Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A

[16:0]

is captured in the address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE

is deserted HIGH.

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A

[16:0]

is captured in the address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized.

Input-

Asynchronous

ZZ "sleep" Input. This active HIGH input places the device in a non-time-critical "sleep" condition
with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ has an internal pull down.

[31:0]

I/O-

Synchronous

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A

[16:0]

during the previous clock rise of the Read cycle. The direction of the pins is controlled

by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ

[31:0]

are placed

in a three-state condition.

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.

Ground

Ground for the core of the device. Should be connected to ground of the system.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.

SSQ

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

MODE

Input-
Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

DDQ

or left

floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an
internal pull up.

No Connects.

DNU

Do Not Use pins. These pins could be left floating or tied to GND.

CY7C1339B

Document #: 38-05141 Rev. *A

Page 5 of 17

Introduction

Functional Overview

) is 3.5 ns

(166-MHz device).

The CY7C1339B supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW

[3:0]

) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE

, CE

are all asserted active, and (3) the Write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE

is HIGH. The address presented to the address inputs

[16:0]

) is stored into the address advancement logic and the

Address Register while being presented to the memory core.
The corresponding data is allowed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.5 ns (166-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE

, CE

are all asserted active. The address

presented to A

[16:0]

is loaded into the address register and the

address advancement logic while being delivered to the RAM
core. The Write signals (GW, BWE, and BW

[3:0]

) and ADV

inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ

[31:0]

inputs is written into the corre-

sponding address location in the RAM core. If GW is HIGH,
then the Write operation is controlled by BWE and BW

[3:0]

signals. The CY7C1339B provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW

[3:0]

) input will selectively write to only the desired

bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.

Because the CY7C1339B is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ

[31:0]

inputs. Doing so will three-state the output

drivers. As a safety precaution, DQ

[31:0]

are automatically

three-stated whenever a Write cycle is detected, regardless of
the state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE

, CE

are all asserted active, and

(4) the appropriate combination of the Write inputs (GW, BWE,
and BW

[3:0]

) are asserted active to conduct a Write to the

desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to
A

[16:0]

is loaded into the address register and the address

advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ

[31:0]

is written into the

corresponding address location in the RAM core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.

Because the CY7C1339B is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ

[31:0]

inputs. Doing so will three-state the output

drivers. As a safety precaution, DQ

[31:0]

are automatically

three-stated whenever a Write cycle is detected, regardless of
the state of OE.

Burst Sequences

The CY7C1339B provides a two-bit wraparound counter, fed
by A

[1:0]

, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.

Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

[1:0]

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