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4-Mb (128K x 32) Pipelined DCD Sync SRAM

CY7C1340F

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05219 Rev. *A

Revised January 19, 2004

Features

· Registered inputs and outputs for pipelined operation
· Optimal for performance (Double-Cycle deselect)

-- Depth expansion without wait state

· 128K × 32-bit common I/O architecture
· 3.3V 5% and +10% core power supply (V

)

· 3.3V / 2.5V I/O supply (V

DDQ

)

· Fast clock-to-output times

-- 2.6 ns (for 250-MHz device)
-- 2.6 ns (for 225-MHz device)
-- 2.8 ns (for 200-MHz device)
-- 3.5 ns (for 166-MHz device)
-- 4.0 ns (for 133-MHz device)
-- 4.5 ns (for 100-MHz device)

· Provide high-performance 3-1-1-1 access rate
· User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

· Separate processor and controller address strobes
· Synchronous self-timed writes
· Asynchronous Output Enable
· JEDEC-standard 100-pin TQFP package and pinout
· "ZZ" Sleep Mode option

Functional Description

[1]

The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.
The CY7C1340F operates from a +3.3V core power supply

while all outputs operate with a +3.3V or a +2.5V supply. All

inputsand outputs are JEDEC-standard JESD8-5-compatible..

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Selection Guide

250 MHz

225 MHz

200 MHz

166 MHz

133 MHz

100 MHz

Unit

Maximum Access Time

2.6

2.8

3.5

4.0

4.5

Maximum Operating Current

325

290

265

240

225

205

Maximum CMOS Standby Current

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

CY7C1340F

Document #: 38-05219 Rev. *A

Page 4 of 17

Pin Descriptions

Pin

TQFP

Type

Description

, A

37,36,32,33

34,35,44,45,

46,47,48,49,

50,81,82,99,

100

Input-

Synchronous

Address Inputs used to select one of the 128K address locations. Sampled at

the rising edge of the CLK if ADSP or ADSC is active LOW, and CE

, and

are sampled active. A

[1:0]

are fed to the two-bit counter.

, BW

93,94,95,96

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes

to the SRAM. Sampled on the rising edge of CLK.

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge

of CLK, a global write is conducted (ALL bytes are written, regardless of the values

on BW

[A:D]

and BWE).

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a byte write.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device. ADSP is ignored if CE

is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the

DQ pins. When LOW, the DQ pins behave as outputs. When deasserted HIGH, DQ

pins are three-stated, and act as input data pins. OE is masked during the first clock

of a read cycle when emerging from a deselected state.

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK, active LOW. When

asserted, it automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active

LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE

deasserted HIGH.

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active

LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized.

Input-

Asynchronous

ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a

non-time-critical "sleep" condition with data integrity preserved. For normal opera-

tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

DQs

52,53,56,57,

58,59,62,63

68,69,72,73,

74,75,78,79

2,3,6,7,8,9,

12,13

18,19,22,23,

24,25,28,29

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by the addresses presented during the previous

clock rise of the read cycle. The direction of the pins is controlled by OE. When OE

is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a

three-state condition.

15,41,65,

Power Supply Power supply inputs to the core of the device.

17,40,67,

Ground

Ground for the core of the device.

DDQ

4,11,20,27,

54,61,70,77

I/O Power

Supply

Power supply for the I/O circuitry.

CY7C1340F

Document #: 38-05219 Rev. *A

Page 5 of 17

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.
The CY7C1340F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW

[A:D]

) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.
Synchronous Chip Selects CE

, CE

and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

is HIGH.

Single Read Accesses
This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

chip selects are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within t

if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, its outputs are always three-stated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive

single read cycles are supported.
The CY7C1340F is a double-cycle deselect part. Once the

SRAM is deselected at clock rise by the chip select and either

ADSP or ADSC signals, its output will three-state immediately

after the next clock rise.

Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) chip select is asserted active. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the memory core.

The write signals (GW, BWE, and BW

[A:D]

) and ADV inputs are

ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQx inputs is written into the corre-

sponding address location in the memory core. If GW is HIGH,

then the write operation is controlled by BWE and BW

[A:D]

signals. The CY7C1340F provides byte write capability that is

described in the Write Cycle Description table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write

input will selectively write to only the desired bytes. Bytes not

selected during a byte write operation will remain unaltered. A

synchronous self-timed write mechanism has been provided

to simplify the write operations.
Because the CY7C1340F is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ

inputs. Doing so will three-state the output drivers.

As a safety precaution, DQ are automatically three-stated

whenever a write cycle is detected, regardless of the state of

OE.

Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and

(4) the appropriate combination of the write inputs (GW, BWE,

and BW

[A:D]

) are asserted active to conduct a write to the

desired byte(s). ADSC triggered write accesses require a

single clock cycle to complete. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the memory core.

The ADV input is ignored during this cycle. If a global write is

conducted, the data presented to the DQ

is written into the

corresponding address location in the memory core. If a byte

write is conducted, only the selected bytes are written. Bytes

not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.
Because the CY7C1340F is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ

inputs. Doing so will three-state the output drivers.

As a safety precaution, DQ

are automatically three-stated

whenever a write cycle is detected, regardless of the state of

OE.

SSQ

5,10,21,26,

55,60,71,76

I/O Ground

Ground for the I/O circuitry.

MODE

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied

to V

or left floating selects interleaved burst sequence. This is a strap pin and

should remain static during device operation. Mode Pin has an internal pull-up.

14,16,38,39,

42,43,66,1,

30,51,80

No Connects. Not internally connected to the die.

Pin Descriptions

(continued)

Pin

TQFP

Type

Description

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