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PRELIMINARY

4-Mbit (256Kx18) Pipelined SRAM

with NoBLTM Architecture

CY7C1352G

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05514 Rev. *A

Revised November 10, 2004

Features

· Pin compatible and functionally equivalent to ZBTTM

devices

· Internally self-timed output buffer control to eliminate

the need to use OE

· Byte Write capability
· 256K x 18 common I/O architecture
· Single 3.3V power supply
· 2.5V / 3.3V I/O Operation
· Fast clock-to-output times
· 2.6 ns (for 250-MHz device)
· 2.8 ns (for 200-MHz device)
· 3.5 ns (for 166-MHz device)
· 4.0 ns (for 133-MHz device)
· Clock Enable (CEN) pin to suspend operation
· Synchronous self-timed writes
· Asynchronous output enable (OE)
· Pb-Free 100 TQFP package
· Burst Capability--linear or interleaved burst order
· ZZ" Sleep Mode Option and Stop Clock option

Functional Description

[1]

The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1352G is equipped with the advanced

No Bus LatencyTM (NoBLTM) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 2.6 ns (250-MHz device).
Write operations are controlled by the two Byte Write Select

(BW

[A:B]

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Notes:

1. For bestpractices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

CE1
CE2
CE3

READ LOGIC

DQs
DQP

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

D1
D0

Q1
Q0

ADV/LD

INPUT

CLK

CEN

WRITE

DRIVERS

Sleep

Control

Logic Block Diagram

PRELIMINARY

CY7C1352G

Document #: 38-05514 Rev. *A

Page 2 of 13

Selection Guide

250 MHz

200 MHz

166 MHz

133 MHz

Unit

Maximum Access Time

2.6

2.8

3.5

4.0

Maximum Operating Current

325

265

240

225

Maximum CMOS Standby Current

Shaded area contains advance information. Please contact your local Cypress sales representative for availability of these parts.

Pin Configuration

NC
NC

DDQ

DQP

DDQ

NC
NC

DDQ

NC
NC
NC

DDQ

NC
NC

DDQ

NC
V

DDQ

DQP

NC
V

DDQ

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

ADV/

CY7C1352G

100-Pin TQFP

BYTE A

BYTE B

PRELIMINARY

CY7C1352G

Document #: 38-05514 Rev. *A

Page 3 of 13

Pin Definitions

Name

I/O

Description

A0, A1, A

Input-

Synchronous

Address Inputs used to select one of the 256K address locations. Sampled at the rising

edge of the CLK. A

[1:0]

are fed to the two-bit burst counter.

[A:B]

Input-

Synchronous

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled

on the rising edge of CLK.

Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

This signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input. Used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,

a new address can be loaded into the device for an access. After being deselected, ADV/LD

should be driven LOW in order to load a new address.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic

block inside the device to control the direction of the I/O pins. When LOW, the DQ pins are

allowed to behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input

data pins. OE is masked during the data portion of a write sequence, during the first clock when

emerging from a deselected state, when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the

SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

Input-

Asynchronous

ZZ "sleep" Input. This active HIGH input places the device in a non-time-critical "sleep"

condition with data integrity preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

DQs

I/O-

Synchronous

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the address during the clock rise of the read cycle. The direction of the pins is

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQ

and DQP

[A:B]

are placed in a tri-state condition. The outputs are

automatically tri-stated during the data portion of a write sequence, during the first clock when

emerging from a deselected state, and when the device is deselected, regardless of the state

of OE.

DQP

[A:B]

I/O-

Synchronous

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ

. During

write sequences, DQP

[A:B]

is controlled by BW

[A:B]

correspondingly.

MODE

Input Strap Pin Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to V

or left floating selects

interleaved burst sequence.

Power Supply

Power supply inputs to the core of the device.

DDQ

I/O Power Supply Power supply for the I/O circuitry.

Ground

Ground for the device.

No Connects. Not internally connected to the die.

PRELIMINARY

CY7C1352G

Document #: 38-05514 Rev. *A

Page 4 of 13

Functional Overview

The CY7C1352G is a synchronous-pipelined Burst SRAM

designed specifically to eliminate wait states during

Write/Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous operations

are qualified with CEN. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (t

) is 2.6 ns (250-MHz

device).
Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW

[A:B]

can be used to

conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.
Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses
A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus, provided OE

is active LOW. After the first clock of the read access the output

buffers are controlled by OE and the internal control logic. OE

must be driven LOW in order for the device to drive out the

requested data. During the second clock, a subsequent

operation (Read/Write/Deselect) can be initiated. Deselecting

the device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signals, its

output will tri-state following the next clock rise.

Burst Read Accesses
The CY7C1352G has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap-around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of chip enables inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Single Write Accesses
Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQs and

DQP[A:B]. In addition, the address for the subsequent access

(Read/Write/Deselect) is latched into the Address Register

(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and

DQP[A:B] (or a subset for byte write operations, see Write

Cycle Description table for details) inputs is latched into the

device and the write is complete.
The data written during the Write operation is controlled by

[A:B]

signals. The CY7C1352G provides byte write

capability that is described in the Write Cycle Description table.

Asserting the Write Enable input (WE) with the selected Byte

Write Select (BW

[A:B]

) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation

will remain unaltered. A synchronous self-timed write

mechanism has been provided to simplify the write operations.

Byte write capability has been included in order to greatly

simplify Read/Modify/Write sequences, which can be reduced

to simple byte write operations.
Because the CY7C1352G is a common I/O device, data

should not be driven into the device while the outputs are

active. The Output Enable (OE) can be deasserted HIGH

before presenting data to the DQs

and DQP

[A:B]

inputs. Doing

so will tri-state the output drivers. As a safety precaution, DQs

and DQP

[A:B]

are automatically tri-stated during the data

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses
The CY7C1352G has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Write operations without reasserting the address inputs.

ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the chip enables (CE

, CE

, and CE

) and WE inputs are

ignored and the burst counter is incremented. The correct

[A:B]

inputs must be driven in each cycle of the burst write

in order to write the correct bytes of data.

PRELIMINARY

CY7C1352G

Document #: 38-05514 Rev. *A

Page 5 of 13

Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CE

, CE

, and CE

, must remain inactive for

the duration of t

ZZREC

after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Truth Table

[2, 3, 4, 5, 6, 7, 8]

Operation

Address

Used

ADV/LD

CEN

CLK

Deselect Cycle

None

L-H

tri-state

Continue Deselect Cycle

None

L-H

tri-state

Read Cycle (Begin Burst)

External

L-H

Data Out (Q)

Read Cycle (Continue Burst)

L-H

Data Out (Q)

NOP/Dummy Read (Begin Burst)

External

L-H

tri-state

Dummy Read (Continue Burst)

L-H

tri-state

Write Cycle (Begin Burst)

External

L-H

Data In (D)

Write Cycle (Continue Burst)

L-H

Data In (D)

NOP/WRITE ABORT (Begin Burst)

None

L-H

tri-state

WRITE ABORT (Continue Burst)

L-H

tri-state

IGNORE CLOCK EDGE (Stall)

Current

L-H

SNOOZE MODE

None

tri-state

Notes:

2. X="Don't Care." H= Logic HIGH, L =Logic LOW. CE stands for ALL Chip Enables active. BWX = L signifies at least one Byte Write Select is active, BWX = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

3. Write is defined by BW

[A:B]

, and WE. See Write Cycle Descriptions table.

4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP

[A:B]

= tri-state when OE

is inactive or when the device is deselected, and DQs and DQP

[A:B]

= data when OE is active.

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