256K x 36/512K x 18 Synchronous
Pipelined Burst SRAM
CY7C1360A
CY7C1362A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05258 Rev. *C
Revised January 18, 2003
Features
Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
Fast clock speed: 225, 200, 166, and 150 MHz
Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V 5% and +10% power supply
3.3V or 2.5V I/O supply
5V-tolerant inputs except I/Os
Clamp diodes to V
SS
at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Multiple chip enables for depth expansion:
three chip enables for A package version and two chip
enables for BG and AJ package versions
Address pipeline capability
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down feature available using ZZ
mode or CE deselect
JTAG boundary scan for BG and AJ package version
Low-profile 119-bump, 14-mm 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1360A and CY7C1362A SRAMs integrate 262,144
36 and 524,288 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), depth-expansion
Chip Enables (CE
2
and CE
3
), burst control inputs (ADSC,
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and
BWE), and global Write (GW). However, the CE
3
chip enable
input is only available for the TA package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the BGA and TQFP AJ package versions, four pins are
used to implement JTAG test capabilities: Test Mode Select
(TMS), Test Data-In (TDI), Test Clock (TCK), and Test
Data-Out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation. The
TA package version does not offer the JTAG capability.
The CY7C1360A and CY7C1362A operate from a +3.3V
power supply. All inputs and outputs are LVTTL-compatible.
Selection Guide
7C1360A-225
7C1362A-225
7C1360A-200
7C1362A-200
7C1360A-166
7C1362A-166
7C1360A-150
7C1362A-150
Unit
Maximum Access Time
2.5
3.0
3.5
3.5
ns
Maximum Operating Current
650
600
520
460
mA
Maximum CMOS Standby Current
10
10
10
10
mA
CY7C1360A
CY7C1362A
Document #: 38-05258 Rev. *C
Page 2 of 28
Notes:
1.
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
2.
CE
3
is for A version only.
Functional Block Diagram--256K 36
[1]
Functional Block Diagram--512K 18
[1]
D
Q
D
Q
BWc
BWE
BWd
BYTE c WRITE
BYTE d WRITE
OUTPUT
REGISTER
OE
by
te c
wr
i
t
e
ADSP
ADSC
Address
Register
Binary
Counter
& Logic
CLR
A
A1-A0
ADV
MODE
256K x 9 x 4
S
R
AM
Ar
r
a
y
O
u
tput
B
u
f
f
er
s
Input
Register
by
te
d wr
i
t
e
DQa,DQb
DQc,DQd
D
Q
D
Q
D
Q
BWa
BWb
GW
BYTE a WRITE
BYTE b WRITE
CLK
by
te
b wr
i
t
e
by
te
a wr
i
t
e
D
Q
D
Q
ENABLE
Power Down Logic
ZZ
16
CE
CE2
CE2
D
Q
D
Q
BWb
BWE
BWa
GW
BYTE b
WRITE
BYTE a
WRITE
OUTPUT
REGISTER
OE
by
te b w
r
i
t
e
ADSP
ADSC
Address
Register
Binary
Counter
& Logic
CLR
A
A1-A0
ADV
MODE
51
2K
x 9 x 2
S
R
AM
Ar
ra
y
O
u
t
put
B
u
ff
er
s
Input
Register
by
te a w
r
i
t
e
DQa,DQb
D
Q
D
Q
D
Q
ENABLE
Power Down Logic
ZZ
17
CE
CE2
CE2
DQa, DQb,
DQc, DQd
DQa, DQb,
CE
3
CE
1
CE
2
BW
a
BW
b
BW
c
BW
d
BWE
CLK
GW
OE
ZZ
ADSP
ADSC
A
ADV
A0-A1
MODE
CE
3
CE
2
BW
a
BW
b
BWE
GW
OE
ZZ
A
CLK
CE
1
ADSP
ADSC
ADV
A0-A1
MODE
[2]
[2]
CY7C1360A
CY7C1362A
Document #: 38-05258 Rev. *C
Page 3 of 28
Pin Configurations
A
A
A
A
A1
A0
TM
S
TDI
V
SS
V
CC
TDO
TC
K
A
A
A
A
A
A
A
DQb
DQb
DQb
V
CCQ
V
SS
DQb
DQb
DQb
DQb
V
SS
V
CCQ
DQb
DQb
V
SS
NC
V
CC
ZZ
DQa
DQa
V
CCQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
CCQ
DQa
DQa
DQa
DQc
DQc
DQc
V
CCQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
CCQ
DQc
DQc
V
CC
NC
V
SS
DQd
DQd
V
CCQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
CCQ
DQd
DQd
DQd
A
A
CE
CE
2
BW
d
BW
c
BW
b
BW
a
A
V
CC
V
SS
CL
K
GW
BW
E
OE
ADS
C
ADS
P
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MO
D
E
100-pin TQFP
AJ Version
NC
A
NC
NC
V
CCQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
CCQ
DQa
DQa
V
SS
NC
V
CC
ZZ
DQa
DQa
V
CCQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
CCQ
V
SS
NC
NC
DQb
DQb
V
SS
V
CCQ
DQb
DQb
V
CC
NC
V
SS
DQb
DQb
V
CCQ
V
SS
DQb
DQb
DQb
NC
V
SS
V
CCQ
NC
NC
NC
A
A
CE
CE
2
NC
NC
BW
b
BW
a
A
V
CC
V
SS
CL
K
GW
BW
E
OE
AD
SC
AD
SP
AD
V
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100-pin TQFP
AJ Version
NC
A
A
A
A
A1
A0
NC
NC
V
SS
V
CC
NC
A
A
A
A
A
A
A
A
DQb
DQb
DQb
V
CCQ
V
SS
DQb
DQb
DQb
DQb
V
SS
V
CCQ
DQb
DQb
V
SS
NC
V
CC
ZZ
DQa
DQa
V
CCQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
CCQ
DQa
DQa
DQa
DQc
DQc
DQc
V
CCQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
CCQ
DQc
DQc
V
CC
NC
V
SS
DQd
DQd
V
CCQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
CCQ
DQd
DQd
DQd
A
A
CE
CE
2
BW
d
BW
c
BW
b
BW
a
CE
3
V
CC
V
SS
CL
K
GW
BW
E
OE
ADS
C
ADS
P
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
100-pin TQFP
NC
A
NC
NC
V
CCQ
V
SS
NC
DQa
DQa
DQa
V
SS
V
CCQ
DQa
DQa
V
SS
NC
V
CC
ZZ
DQa
DQa
V
CCQ
V
SS
DQa
DQa
NC
NC
V
SS
V
CCQ
NC
NC
NC
NC
NC
NC
V
CCQ
V
SS
NC
NC
DQb
DQb
V
SS
V
CCQ
DQb
DQb
V
CC
NC
V
SS
DQb
DQb
V
CCQ
V
SS
DQb
DQb
DQb
NC
V
SS
V
CCQ
NC
NC
NC
A
A
CE
CE
2
NC
NC
BW
b
BW
a
CE
3
V
CC
V
SS
CL
K
GW
BW
E
OE
AD
SC
AD
SP
AD
V
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100-pin TQFP
A Version
NC
A
A
A
A
A1
A0
TMS
TD
I
V
SS
V
CC
TD
O
TC
K
A
A
A
A
A
A
A
MO
D
E
A
A
A
A
A1
A0
NC
NC
V
SS
V
CC
NC
A
A
A
A
A
A
A
A
MO
D
E
A Version
512K 18 100-p
i
n TQFP
CY7C1362A
CY7C1360A
256K 36 100-p
i
n TQFP
Top View
Top View
CY7C1360A
CY7C1362A
Document #: 38-05258 Rev. *C
Page 4 of 28
Pin Configurations
(continued)
CY7C1360A 256K 36 119-ball BGA Top V
i
ew
1
2
3
4
5
6
7
A
V
CCQ
A
A
ADSP
A
A
V
CCQ
B
NC
CE
2
A
ADSC
A
A
NC
C
NC
A
A
V
CC
A
A
NC
D
DQc
DQc
V
SS
NC
V
SS
DQb
DQb
E
DQc
DQc
V
SS
CE
V
SS
DQb
DQb
F
V
CCQ
DQc
V
SS
OE
V
SS
DQb
V
CCQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
V
SS
GW
V
SS
DQb
DQb
J
V
CCQ
V
CC
NC
V
CC
NC
V
CC
V
CCQ
K
DQd
DQd
V
SS
CLK
V
SS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
V
CCQ
DQd
V
SS
BWE
V
SS
DQa
V
CCQ
N
DQd
DQd
V
SS
A1
V
SS
DQa
DQa
P
DQd
DQd
V
SS
A0
V
SS
DQa
DQa
R
NC
A
MODE
V
CC
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
V
CCQ
TMS
TDI
TCK
TDO
NC
V
CCQ
1
2
3
4
5
6
7
A
V
CCQ
A
A
ADSP
A
A
V
CCQ
B
NC
CE
2
A
ADSC
A
CE
3
NC
C
NC
A
A
V
CC
A
A
NC
D
DQb
NC
V
SS
NC
V
SS
DQa
NC
E
NC
DQb
V
SS
CE
V
SS
NC
DQa
F
V
CCQ
NC
V
SS
OE
V
SS
DQa
V
CCQ
G
NC
DQb
BWb
ADV
V
SS
NC
DQa
H
DQb
NC
V
SS
GW
V
SS
DQa
NC
J
V
CCQ
V
CC
NC
V
CC
NC
V
CC
V
CCQ
K
NC
DQb
V
SS
CLK
V
SS
NC
DQa
L
DQb
NC
V
SS
NC
BWa
DQa
NC
M
V
CCQ
DQb
V
SS
BWE
V
SS
NC
V
CCQ
N
DQb
NC
V
SS
A1
V
SS
DQa
NC
P
NC
DQb
V
SS
A0
V
SS
NC
DQa
R
NC
A
MODE
V
CC
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
V
CCQ
TMS
TDI
TCK
TDO
NC
V
CCQ
CY7C1362A 512K 18 119-ball BGA Top View
CY7C1360A
CY7C1362A
Document #: 38-05258 Rev. *C
Page 5 of 28
256K 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A, 3B, 5B,
6B, 2C, 3C, 5C, 6C,
2R, 6R, 3T, 4T, 5T
37
36
35, 34, 33, 32, 100,
99, 82, 81, 44, 45,
46, 47, 48, 49, 50
92 (AJ Version)
43 (A Version)
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write: A byte Write is LOW for a Write cycle and
HIGH for a Read cycle. BWa controls DQa. BWb controls
DQb. BWc controls DQc. BWd controls DQd. Data I/O are
high impedance if either of these inputs are LOW, condi-
tioned by BWE being LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit
Write to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the rising
edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip
enables, Write control, and burst control inputs on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock's rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
2B
97
CE
2
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable
the device.
(not available for
PBGA)
92
(for A version only)
CE
3
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input
enables the data output drivers.
4G
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
4A
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input,
along with CE being LOW, causes a new external address
to be registered and a Read cycle is initiated using the
new address.
4B
85
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input
causes the device to be deselected or selected along with
new external address to be registered. A Read or Write
cycle is initiated depending upon Write control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
7T
64
ZZ
Input-
Asynchronous
Sleep: This active HIGH input puts the device in low
power consumption standby mode. For normal operation,
this input has to be either LOW or NC (No Connect).
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