256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 11, 2001
1CY7C1361A
Features
Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
Fast clock speed: 150, 133, 117, and 100 MHz
1 ns set-up time and hold time
Fast OE access times: 3.5 ns and 4.0 ns
3.3V 5% and +10% power supply
3.3V or 2.5V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to V
SS
at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
Address pipeline capability
Address, data and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
JTAG boundary scan for B and T package version
Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The GVT71256B36/CY7C1361A and GVT71512B18/
CY7C1363A SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a positive-
edge-triggered Clock Input (CLK). The synchronous inputs in-
clude all addresses, all data inputs, address-pipelining Chip
Enable (CE), depth-expansion Chip Enables (CE
2
and CE
2
),
Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables
(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).
However, the CE
2
chip enable input is only available for TA(GV-
TI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The GVT71256B36 and GVT71512B18 operate from a +3.3V
power supply. All inputs and outputs are LVTTL compatible.
Selection Guide
7C1361A-150
7C1363A-150
71256B36-6
71512B18-6
7C1361A-133
7C1363A-133
71256B36-6.5
71512B18-6.5
7C1361A-117
7C1363A-117
71256B36-7
71512B18-7
7C1361A-100
7C1363A-100
71256B36-8
71512B18-8
Maximum Access Time (ns)
6.0
6.5
7.0
8.0
Maximum Operating Current (mA)
400
360
320
270
Maximum CMOS Standby Current (mA)
10
10
10
10
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
3
Pin Configurations
CY7C1361A/GVT71256B36
100-pin TQFP
TA version
100 99 98 97 96 95 94 93 92 91 90 89 88
1
2
3
4
5
6
7
8
9
10
31 32 33 34 35 36 37 38 39 40 41 42 43
87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44 45 46 47 48 49 50
A
A
CE#
ADSC#
ADSP#
ADV#
CLK
OE#
A
A
VCC
VSS
GW#
BWE#
CE2#
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
DQa
DQa
VCCQ
VSS
DQa
DQa
VSS
NC
VCC
ZZ
A
A
A
A
A1
A0
VSS
VCC
A
A
A
A
A
MODE
NC
NC
NC
A
A
A
CE2
BWd#
BWc#
BWb#
BWa#
VCCQ
VSS
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
DQa
VSS
VCCQ
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
DQd
DQd
VCCQ
VSS
DQd
DQd
VSS
NC
VCC
NC
VCCQ
VSS
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
VSS
VCCQ
100-pin TQFP
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8
1
2
3
4
5
6
7
8
9
1 0
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3
8 7 8 6 8 5 8 4 8 3 8 2 8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
4 4 4 5 4 6 4 7 4 8 4 9 5 0
A
A
CE#
ADSC#
ADSP#
ADV#
CLK
OE#
A
A
VCC
VSS
GW#
BWE#
A
D Q b
D Q b
D Q b
V S S
V C C Q
D Q b
D Q b
D Q a
D Q a
V C C Q
V S S
D Q a
D Q a
V S S
N C
V C C
Z Z
A
A
A
A
A1
A0
VSS
VCC
A
A
A
A
A
MODE
TMS
TDI
TDO
TCK
A
A
CE2
BWd#
BWc#
BWb#
BWa#
V C C Q
V S S
D Q b
D Q b
D Q b
D Q b
D Q a
D Q a
D Q a
D Q a
D Q a
V S S
V C C Q
D Q c
D Q c
D Q c
V S S
V C C Q
D Q c
D Q c
D Q d
D Q d
V C C Q
V S S
D Q d
D Q d
V S S
N C
V C C
N C
V C C Q
V S S
D Q c
D Q c
D Q c
D Q c
D Q d
D Q d
D Q d
D Q d
D Q d
V S S
V C C Q
T(AJ) Package Version
TA(A) Package Version
256Kx36 100-Pin TQFP
100-pin TQFP
10
0
99 98 97 96 95 94 93 92 91 90 89 88
1
2
3
4
5
6
7
8
9
10
31 32 33 34 35 36 37 38 39 40 41 42 43
87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44 45 46 47 48 49 50
A
A
CE#
BWb#
BWa#
ADSC#
ADSP#
ADV#
CLK
OE#
A
A
VCC
VSS
GW#
BWE#
A
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
DQa
VCCQ
VSS
DQa
DQa
A
NC
NC
VCCQ
VSS
NC
NC
NC
VSS
VCCQ
NC
NC
NC
VSS
NC
VCC
ZZ
DQb
DQb
VSS
VCCQ
DQb
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
NC
NC
VCCQ
VSS
NC
NC
NC
VCC
NC
VSS
NC
VSS
VCCQ
NC
NC
NC
A
A
A
A
A1
A0
VSS
VCC
A
A
A
A
A
MODE
A
A
CE2
NC
NC
TMS
TDI
TDO
TCK
CY7C1363A/GVT71512B18
T(AJ) Package Version
TA(A) Package Version
100-pin TQFP
TA version
100 99 98 97 96 95 94 93 92 91 90 89 88
1
2
3
4
5
6
7
8
9
10
31 32 33 34 35 36 37 38 39 40 41 42 43
87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44 45 46 47 48 49 50
A
A
CE#
BWb#
BWa#
ADSC#
ADSP#
ADV#
CLK
OE#
A
A
VCC
VSS
GW#
BWE#
CE2#
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
DQa
VCCQ
VSS
DQa
DQa
A
NC
NC
VCCQ
VSS
NC
NC
NC
VSS
VCCQ
NC
NC
NC
VSS
NC
VCC
ZZ
DQb
DQb
VSS
VCCQ
DQb
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
NC
NC
VCCQ
VSS
NC
NC
NC
VCC
NC
VSS
NC
VSS
VCCQ
NC
NC
NC
A
A
A
A
A1
A0
VSS
VCC
A
A
A
A
A
MODE
A
A
CE2
NC
NC
NC
NC
NC
A
512Kx18 100-Pin TQFP
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
5
256K x 36 Pin Descriptions
x36 PBGA Pins
x36 QFP Pins
Pin
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C,
3C, 5C, 6C, 2R,
6R, 3T, 4T, 5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
92 (A/T version)
43 (AJ/TA ver-
sion)
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the set-
up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for
a READ cycle. BWa controls DQa. BWb controls DQb. BWc con-
trols DQc. BWd controls DQd. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write operations
and must meet the set-up and hold times around the rising edge
of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit WRITE to
occur independent of the BWE and BWn lines and must meet the
set up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All syn-
chronous inputs must meet set up and hold times around the
clock's rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device
and to gate ADSP.
2B
97
CE
2
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
(not available for
PBGA)
92 (for AJ/TA
version only)
CE
2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device.
Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
4G
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with CE
being LOW, causes a new external address to be registered and
a READ cycle is initiated using the new address.
4B
85
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes device
to be deselected or selected along with new external address to
be registered. A READ or WRITE cycle is initiated depending
upon write control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin
selects linear burst. A NC or HIGH on this pin selects interleaved
burst.
7T
64
ZZ
Input-
Asynchro-
nous
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
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