E
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
DS1643
Nonvolatile Timekeeping RAM
DS1643
041697 1/11
FEATURES
Form, fit, and function compatible with the MK48T08
Timekeeping RAM
Integrated NV SRAM, real time clock, crystal, power
fail control circuit and lithium energy source
Standard JEDEC bytewide 8K x 8 static RAM pinout
Clock registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
Totally nonvolatile with over 10 years of operation in
the absence of power
Access times of 120 ns and 150 ns
Quartz accuracy
1 minute a month @ 25
C, factory
calibrated
BCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to
2100
Powerfail write protection allows for
10% V
CC
power supply tolerance
ORDERING INFORMATION
DS1643XXX
120 120 ns access
150 ns access
150
28pin DIP module
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
CE2
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
WE
OE
CE
28PIN ENCAPSULATED PACKAGE
(700 MIL EXTENDED)
DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a
full function real time clock which are both accessible in
a bytewide format. The nonvolatile time keeping RAM is
pin and function equivalent to any JEDEC standard
8K x 8 SRAM. The device can also be easily substituted
in ROM, EPROM and EEPROM sockets providing read/
write nonvolatility and the addition of the real time clock
function. The real time clock information resides in the
eight uppermost RAM locations. The RTC registers
contain year, month, date, day, hours, minutes, and se-
conds data in 24 hour BCD format. Corrections for the
day of the month and leap year are made automatically.
The RTC clock registers are double buffered to avoid
access of incorrect data that can occur during clock up-
date cycles. The double buffered system also prevents
time loss as the timekeeping countdown continues un-
abated by access to time register data. The DS1643
also contains its own powerfail circuitry which dese-
lects the device when the V
CC
supply is in an out of toler-
ance condition. This feature prevents loss of data from
unpredictable system operation brought on by low V
CC
as errant access and update cycles are avoided.
DS1643
041697 2/11
PIN DESCRIPTION
A0A12
Address Input
CE
Chip Enable
OE
Output Enable
WE
Write Enable
NC
No Connection
V
CC
+5 Volts
GND
Ground
DQ0-DQ7
Data Input/Output
CLOCK OPERATIONSREADING THE
CLOCK
While the double buffered register structure reduces the
chance of reading incorrect data, internal updates to the
DS1643 clock registers should be halted before clock
data is read to prevent reading of data in transition.
However, halting the internal clock register updating
process does not affect clock accuracy. Updating is
halted when a one is written into the read bit, the seventh
most significant bit in the control register. As long as a
one remains in that position, updating is halted. After a
halt is issued, the registers reflect the count, that is day,
date, and time that was current at the moment the halt
command was issued. However, the internal clock reg-
isters of the double buffered system continue to update
so that the clock accuracy is not affected by the access
of data. All of the DS1643 registers are updated simul-
taneously after the clock status is reset. Updating is
within a second after the read bit is written to zero.
DS1643 BLOCK DIAGRAM Figure 1
OSCILLATOR AND
CLOCK COUNTDOWN
CHAIN
POWER MONITOR,
SWITCHING, AND
WRITE PROTECTION
V
CC
POWER GOOD
CLOCK
REGISTERS
8K X 8 NV SRAM
CE
WE
A0A12
DQ0DQ7
32.768 KHz
+
OE
V
BAT
DS1643
041697 3/11
DS1643 TRUTH TABLE Table 1
V
CC
CE
CE2
OE
WE
MODE
DQ
POWER
5 VOLTS
10%
V
IH
X
X
X
DESELECT
HIGH Z
STANDBY
5 VOLTS
10%
X
V
IL
X
X
DESELECT
HIGH Z
STANDBY
5 VOLTS
10%
V
IL
V
IH
X
V
IL
WRITE
DATA IN
ACTIVE
V
IL
V
IH
V
IL
V
IH
READ
DATA OUT
ACTIVE
V
IL
V
IH
V
IH
V
IH
READ
HIGH Z
ACTIVE
<4.5 VOLTS
>V
BAT
X
X
X
X
DESELECT
HIGH Z
CMOS STANDBY
<V
BAT
X
X
X
X
DESELECT
HIGH Z
DATA RETENTION
MODE
SETTING THE CLOCK
The 8bit of the control register is the write bit. Setting
the write bit to a one, like the read bit, halts updates to
the DS1643 registers. The user can then load them with
the correct day, date and time data in 24 hour BCD for-
mat. Resetting the write bit to a zero then transfers
those values to the actual clock counters and allows
normal operation to resume.
STOPPING AND STARTING THE CLOCK
OSCILLATOR
The clock oscillator may be stopped at any time. To in-
crease the shelf life, the oscillator can be turned off to
minimize current drain from the battery. The OSC bit is
the MSB for the seconds registers. Setting it to a 1 stops
the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the
frequency test bit is set to logic "1" and the oscillator is
running, the LSB of the seconds register will toggle at
512 Hz. When the seconds register is being read, the
DQ0 line will toggle at the 512 Hz frequency as long as
conditions for access remain valid (i.e., CE low, OE low,
CE2 high, and address for seconds register remain valid
and stable).
CLOCK ACCURACY
The DS1643 is guaranteed to keep time accuracy to
within
1 minute per month at 25
C. The clock is cali-
brated at the factory by Dallas Semiconductor using
special calibration nonvolatile tuning elements. The
DS1643 does not require additional calibration and tem-
perature deviations will have a negligible effect in most
applications. For this reason, methods of field clock cal-
ibration are not available and not necessary. Attempts
to calibrate the clock that may be used with similar de-
vice types (MK48T08 family) will not have any effect
even though the DS1643 appears to accept calibration
data.
DS1643
041697 4/11
DS1643 REGISTER MAP BANK1 Table 2
ADDRESS
DATA
FUNCTION
ADDRESS
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION
1FFF
YEAR
0099
1FFE
X
X
X
MONTH
0112
1FFD
X
X
DATE
0131
1FFC
X
FT
X
X
X
DAY
0107
1FFB
X
X
HOUR
0023
1FFA
X
MINUTES
0059
1FF9
OSC
SECONDS
0059
1FF8
W
R
X
X
X
X
X
X
CONTROL
A
OSC = STOP BIT
R
=
READ BIT
FT =
FREQUENCY TEST
W
= WRITE BIT
X
=
UNUSED
NOTE:
All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write
enable) is high and CE (chip enable) is low. The device
architecture allows ripple-through access to any of the
address locations in the NV SRAM. Valid data will be
available at the DQ pins within t
AA
after the last address
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
chip enable access (t
CEA
) or at output enable access
time (t
OEA
). The state of the data input/output pins (DQ)
is controlled by CE and OE. If the outputs are activated
before t
AA
, the data lines are driven to an intermediate
state until t
AA
. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for
output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE
are in their active state. The start of a write is referenced
to the latter occurring transition of WE or CE. The ad-
dresses must be held valid throughout the cycle. CE or
WE must return inactive for a minimum of t
WR
prior to
the initiation of another read or write cycle. Data in must
be valid t
DS
prior to the end of write and remain valid for
t
DH
afterward. In a typical application, the OE signal will
be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by
the address inputs. A low transition on WE will then dis-
able the outputs t
WEZ
after WE goes active.
DS1643
041697 5/11
DATA RETENTION MODE
When V
CC
is within nominal limits (V
CC
> 4.5 volts) the
DS1643 can be accessed as described above by read
or write cycles. However, when V
CC
is below the pow-
erfail point V
PF
(point at which write protection occurs)
the internal clock registers and RAM is blocked from ac-
cess. This is accomplished internally by inhibiting ac-
cess via the CE and CE2 signals. When V
CC
falls below
the level of the internal battery supply, power input is
switched from the V
CC
pin to the internal battery and
clock activity, RAM, and clock data are maintained from
the battery until V
CC
is returned to nominal level.
INTERNAL BATTERY LONGEVITY
The DS1643 has a self contained lithium power source
that is designed to provide energy for clock activity, and
clock and RAM data retention when the V
CC
supply is
not present. The capability of this internal power supply
is sufficient to power the DS1643 continuously for the
life of the equipment in which it is installed. For specifi-
cation purposes, the life expectancy is 10 years at 25
C
with the internal clock oscillator running in the absence
of V
CC
power. The DS1643 is shipped from Dallas
Semiconductor with the clock oscillator turned off, so
the expected life should be considered to start from the
time the clock oscillator is first turned on. Actual life ex-
pectancy of the DS1643 will be much longer than 10
years since no internal lithium battery energy is con-
sumed when V
CC
is present. In fact, in most applica-
tions, the life expectancy of the DS1643 will be approxi-
mately equal to the shelf life (expected useful life of the
lithium battery with no load attached) of the lithium bat-
tery which may prove to be as long as 20 years.
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