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082800

FEATURES

32-bit counter

2-wire serial interface

Automatic power-fail detect and switch
circuitry

Power-fail reset output

Low-voltage oscillator operation (1.3V min.)

Trickle charge capability

ORDERING INFORMATION

DS1672X-X

2.0V operation

3.0V operation

33 3.3V operation

blank

8-pin DIP

8-pin SOIC

8-pin �SOP

PIN ASSIGNMENT

PIN DESCRIPTION

CC,

BACKUP

- Power Supply Inputs

GND

- Ground

X1, X2

- 32.768 kHz crystal pins

SCL

- Serial clock

SDA

- Serial data

RST

- Reset output

DESCRIPTION

The DS1672 incorporates a 32-bit counter and power monitoring functions. The 32-bit counter is
designed to count seconds and can be used to derive time of day, week, month, month, and year by using
a software algorithm. A precision temperature-compensated reference and comparator circuit monitors
the status of V

. When an out-of-tolerance condition occurs, an internal power-fail signal is generated

which forces the reset to the active state. When V

returns to an in-tolerance condition, the reset signal

is kept in the active state for 250 ms to allow the power supply and processor to stabilize.

OPERATION

The block diagram in Figure 1 shows the main elements of the DS1672. As shown, communications to
and from the DS1672 occur serially over a 2-wire bi-directional bus. The DS1672 operates as a slave
device on the serial bus. Access is obtained by implementing a START condition and providing a device
identification code followed by a register address. Subsequent registers can be accessed sequentially until
a STOP condition is executed.

DS1672

Low Voltage Serial Timekeeping Chip

PRELIMINARY

RST

SCL

SDA

BACKUP

GND

DS1672

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DS1672 BLOCK DIAGRAM Figure 1

ADDRESS MAP

The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h - 03h). The control
register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated
in Figure 2. If the master continues to send or request more data after the address pointer has reached
05h, the address pointer will wrap around to location 00h.

DS1672 REGISTERS Figure 2

Address B7

Function

00h

Counter
Byte 1

01h

Counter
Byte 2

02h

Counter
Byte 3

03h

Counter
Byte 4

04h

EOSC

Control

05h

TCS

Trickle
Charger

DATA RETENTION MODE

The device is fully accessible and data can be written and ready only when V

is greater than V

However, when V

falls below V

, (point at which write protection occurs) the internal clock registers

are blocked from any access. If V

is less than V

BACKUP

, the device power is switched from V

BACKUP

when V

drops below V

. If V

is greater than V

BACKUP

, the device power is switched from

to V

BACKUP

when V

drops below V

BACKUP

. The registers are maintained from the V

BACKUP

source

until V

is returned to nominal levels.

32-BIT

COUNTER

(4 BYTES)

SERIAL BUS

INTERFACE

OSCILLATOR

AND DIVIDER

POWER

CONTROL

ADDRESS

CONTROL

LOGIC

BACKUP

GND

SCL

SDA

CONTROL

TRICKLE CHARGER

RST

DS1672

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OSCILLATOR CONTROL

The

EOSC

bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when

set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is placed into a low-power standby mode with a current drain of less than 200 nanoamps when in
back-up mode. When the DS1672 is powered by V

CC,

the oscillator is always on regardless of the status

of the

EOSC

bit; however, the counter is incremented only when

EOSC

is a logic 0.

CRYSTAL SELECTION

A standard 32.768 kHz quartz crystal should be directly connected to the X1 and X2 oscillator pins. The
crystal selected for use should have a specified load capacitance (C

) of 6 pF. For more information on

crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal
Considerations with Dallas Real Time Clocks."

MICROPROCESSOR MONITOR

A temperature-compensated comparator circuit monitors the level of V

. When V

falls to the power-

fail trip point, the

RST

signal (open drain) is pulled active. When V

returns to nominal levels, the

RST

signal is kept in the active state for 250 ms (typically) to allow the power supply and microprocessor to
stabilize. Note, however, that if the

EOSC

bit is set to a logic 1 (to disable the oscillator during write

protection), the reset signal will be kept in an active state for 250 ms plus the start-up time of the
oscillator.

TRICKLE CHARGER

The trickle charger is controlled by the trickle charge register. The simplified schematic of Figure 3
shows the basic components of the trickle charger. The trickle charge select (TCS) bit (bits 4-7) controls
the selection of the trickle charger. In order to prevent accidental enabling, only a pattern on 1010 will
enable the trickle charger. All other patterns will disable the trickle charger. The DS1672 powers up
with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select whether or not a diode is
connected between V

and V

BACKUP

. If DS is 01, no diode is selected or if DS is 10, a diode is selected.

The RS bits (bits 0-1) select whether a resistor is connected between V

and V

BACKUP

and

what the value

of the resistor is. The resistor selected by the resistor select (RS) bits and the diode selected by the diode
select (DS) bits are as follows:

TCS

Function

Disabled

No diode, 100

resistor

One diode, 100

resistor

No diode, 2 k

resistor

One diode, 2 k

resistor

No diode, 4 k

resistor

One diode, 4 k

resistor

DS1672

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Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 3 volt is applied to V

and a super cap is

connected to V

BACKUP

. Also assume that the trickle charger has been enabled with a diode and resistor R2

between V

and V

BACKUP

. The

maximum current I

max

would therefore be calculated as follows:

max

= (3.0V � diode drop) / R2

~ (3.0V � 0.7V) / 2 k

~ 1.2 mA

Obviously, as the super cap changes, the voltage drop between V

and V

BACKUP

will decrease and

therefore the charge current will decrease.

DS1672 PROGRAMMABLE TRICKLE CHARGER Figure 3

1 OF 16 SELECT

NOTE: ONLY 1010 ENABLES

1 OF 2

SELECT

1 OF 3

SELECT

TCS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

100

TRICKLE CHARGE REGISTER

TCS = TRICKLE CHARGER SELECT
DS = DIODE SELECT
RS = RESISTOR SELECT

BACKUP

DS1672

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2-WIRE SERIAL DATA BUS

The DS1672 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a "master." The devices that are controlled by the master are "slaves." The
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1672 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (see Figure 4).
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.

Stop data transfer: A change in the state of the data line from low to high, while the clock line is high,
defines a STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between the START and the STOP conditions is not limited, and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.

Электронный компонент: DS1672S-33