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011800
FEATURES
8051-compatible microcontroller adapts to its
task
-
32K, 64K, or 128K bytes of nonvolatile
SRAM for program and/or data storage
-
In-system programming via on-chip serial
port
-
Capable of modifying its own program or
data memory in the end system
-
Provides separate Byte-wide bus for
peripherals
-
Performs CRC-16 check of NV RAM
memory
High-reliability operation
-
Maintains all nonvolatile resources for
over 10 years in the absence of power
-
Power-fail reset
-
Early Warning Power-fail Interrupt
-
Watchdog Timer
-
Lithium backed memory remembers
system state
-
Precision reference for power monitor
Fully 8051-compatible
-
128 bytes scratchpad RAM
-
Two timer/counters
-
On-chip serial port
-
32 parallel I/O port pins
Permanently powered real time clock
PIN ASSIGNMENT
DESCRIPTION
The DS2251T 128k Soft Microcontroller Module is an 8051-compatible microcontroller module based on
nonvolatile RAM technology. It is designed for systems that need large quantities of nonvolatile memory.
Like other members of the Secure Microcontroller family, it provides full compatibility with the 8051
instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can
program, then reprogram the microcontroller while in-system. The application software can even change
its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc.
In addition, by using NV RAM, the DS2251T is ideal for data logging applications. The powerful real
time clock includes interrupts for time stamp and date. It keeps time to one-hundredth of seconds using its
onboard 32 kHz crystal.
DS2251(T)
128k Soft Microcontroller Module
www.dalsemi.com
72
1
72-Pin SIMM
DS2251T
2 of 20
The DS2251T provides the benefits of NV RAM without using I/O resources. Between 32 kbytes and 128
kbytes of onboard NV RAM are available. A non-multiplexed Byte-wide address and data bus is used for
memory access. This bus, which is available at the connector, can perform all memory access and also
provide decoded chip enables for off-board memory mapped peripherals. This leaves the 32 I/O port pins
free for application use.
The DS2251T provides high-reliability operation in portable systems or systems with unreliable power.
These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and
Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room
temperature in the absence of power.
A user loads programs into the DS2251T via its on-chip serial Bootstrap loader. This function supervises
the loading of software into NV RAM, validates it, then becomes transparent to the user. Software is
stored in onboard CMOS SRAM. Using its internal Partitioning, the DS2251T can divide a common
RAM into user-selectable program and data segments. This Partition can be selected at program loading
time, but can be modified anytime later. The microprocessor will decode memory access to the SRAM,
access memory via its Byte-wide bus and write-protect the memory portion designated as program
(ROM).
ORDERING INFORMATION
PART NUMBER
RAM SIZE
MAX CRYSTAL
SPEED
TIMEKEEPING?
DS2251T-32-16
32 kbytes
16 MHz
Yes
DS2251T-64-16
64 kbytes
16 MHz
Yes
DS2251T-128-16
128 kbytes
16 MHz
Yes
Operating information is contained in the User's Guide section of the Secure Microcontroller Data Book.
This data sheet provides ordering information, pinout, and electrical specifications.
DS2251T
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DS2251(T) BLOCK DIAGRAM Figure 1
DS2251T
4 of 20
PIN ASSIGNMENT
1
P1.0
19
XTAL2
37
P0.2
55
INTB
2
P1.1
20
GND
38
P0.1
56
BD0
3
P1.2
21
P2.0
39
P0.0
57
BD1
4
P1.3
22
P2.1
40
V
CC
58
BD2
5
P1.4
23
P2.2
41
BA0
59
BD3
6
P1.5
24
P2.3
42
BA1
60
BD4
7
P1.6
25
P2.4
43
BA2
61
BD5
8
P1.7
26
P2.5
44
BA3
62
BD6
9
RST
27
P2.6
45
BA4
63
BD7
10
P3.0 RXD
28
P2.7
46
BA5
64
R/
W
11
P3.1 TXD
29
PSEN
47
BA6
65
PF
12
P3.2
INT0
30
ALE
48
BA7
66
PE3
13
P3.3
INT1
31
PROG
49
BA8
67
PE4
14
P3.4 T0
32
P0.7
50
BA9
68
INTP
15
P3.5 T1
33
P0.6
51
BA10
69
INTA
16
P3.6
WR
34
P0.5
52
BA11
70
SQW
17
P3.7
RD
35
P0.4
53
BA12
71
VRST
18
XTAL1
36
P0.3
54
BA13
72
BA15
PIN DESCRIPTION
PIN
DESCRIPTION
39-32
P0.0 - P0.7. General purpose I/O Port 0. This port is open-drain and cannot drive a logic 1.
It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus.
When used in this mode, it does not require pullups.
1-8
P1.0 - P1.7. General purpose I/O Port 1.
21-28
P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address
bus.
10
P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on-
board UART. This pin should NOT be connected directly to a PC COM port.
11
P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on-
board UART. This pin should NOT be connected directly to a PC COM port.
12
P3.2
INT0
. General purpose I/O port pin 3.2. Also serves as the active low External
Interrupt 0.
13
P3.3
INT1
. General purpose I/O port pin 3.3. Also serves as the active low External
Interrupt 1.
14
P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
15
P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
DS2251T
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PIN
DESCRIPTION
16
P3.6
WR
. General purpose I/O port pin. Also serves as the write strobe for Expanded bus
operation.
17
P3.7
RD
. General purpose I/O port pin. Also serves as the read strobe for Expanded bus
operation.
9
RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This
pin is pulled down internally, can be left unconnected if not used. An RC power-on reset
circuit is not needed and is NOT recommended.
29
PSEN
- Program Store Enable. This active low signal is used to enable an external program
memory when using the Expanded bus. It is normally an output and should be unconnected
if not used.
30
ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded
Address/Data bus on Port 0. This pin is normally connected to the clock input on a `373
type transparent latch.
19, 18
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
20
GND - Logic ground.
40
V
CC
- +5V.
72
BA15 - Monitor test point to reflect the logical value of A15. Not needed for memory
access.
54-41
BA13 - 0. Byte-wide Address bus bits 13-0. This bus is combined with the non-multiplexed
data bus (BD7-0) to access onboard NV SRAM and off-board peripherals. Peripheral
decoding is performed using
PE3
and
PE4
. These are on 16k boundaries, so BA14 or BA15
are not needed. Read/write access is controlled by R/
W
. BA13-0 connect directly to
memory mapped peripherals.
63-56
BD7 - 0. Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the
non-multiplexed address bus (BA14-0) to access on-board NV SRAM and off-board
peripherals.
64
R/
W
- Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide
bus. It is controlled by the memory map and Partition. The blocks selected as Program
(ROM) will be write-protected. This signal is also used for the write enable to off-board
peripherals.
66
PE3
- Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
when the PES bit is set to a logic 1.
PE3
is not lithium backed and can be connected to any
type of peripheral function.
67
PE4
- Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to a logic 1.
PE4
is not lithium backed and can be connected to any
type of peripheral function.
31
PROG
- Invokes the Bootstrap loader on a falling edge. This signal should be debounced so
that only one edge is detected. If connected to ground, the micro will enter Bootstrap
loading on power-up. This signal is pulled up internally.
DS2251T
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PIN
DESCRIPTION
71
VRST
- This I/O pin (open-drain with internal pullup) indicates that the power supply (V
CC
)
has fallen below the V
CCMIN
level and the micro is in a reset state. When this occurs, the
DS2251T will drive this pin to a logic 0. Because the micro is lithium backed, this signal is
guaranteed even when V
CC
=0V. Because it is an I/O pin, it will also force a reset if pulled
low externally. This allows multiple parts to synchronize their power-down resets.
65
PF
- This output goes to a logic 0 to indicate that the micro has switched to lithium backup.
It corresponds to V
CC
< V
LI
. Because the micro is lithium backed, this signal is guaranteed
even when V
CC
=0V.
55
INTB
-
INTB
from the real time clock. This output may be connected to a micro interrupt
input.
68
INTP
-
INTP
from the real time clock. This open-drain output requires a pullup and may be
connected to a micro interrupt input.
69
INTA
-
INTA
from the real time clock. This output may be connected to a micro interrupt
input.
70
SQW - SQW output from the DS1283 Real Time Clock. Can be programmed to output an
1024 Hz square wave.
INSTRUCTION SET
The DS2251T executes an instruction set that is object code compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS2251T.
A complete description of the instruction set and operation are provided in the User's Guide section of the
Secure Microcontroller Data Book.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the DS2251T. The entire 64k of program and 64k of
data are available to the Byte-wide bus. This preserves the I/O ports for application use. The user controls
the portion of memory that is actually mapped to the Byte-wide bus by selecting the Program Range and
Data Range. Any area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 and 2.
An alternate configuration allows dynamic Partitioning of a 64k space as shown in Figure 3. Selecting
PES=1 provides access to the real time clock on the DS2251T and enables
PE3
and
PE4
for peripheral
access as shown in Figure 4. These selections are made using Special Function Registers. The memory
map and its controls are covered in detail in the User's Guide section of the Secure Microcontroller Data
Book.
DS2251T
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DS2251T MEMORY MAP IN NON-PARTITIONABLE MODE (PM=1) Figure 2
DS2251T MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3
DS2251T
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DS2251T MEMORY MAP WITH (PES=1) Figure 4
POWER MANAGEMENT
The DS2251T monitors V
CC
to provide Power-fail Reset, early warning Power-fail Interrupt, and switch-
over to lithium backup. It uses an internal band-gap reference in determining the switch points. These are
called V
PFW
, V
CCMIN
, and V
LI
respectively. When V
CC
drops below V
PFW
, the DS2251T will perform an
interrupt vector to location 2Bh if the power-fail warning is enabled. Full processor operation continues
regardless. When power falls further to V
CCMIN
, the DS2251T invokes a reset state. No further code
execution will be performed unless power rises back above V
CCMIN
. All decoded chip enables and the
R/
W
signal go to an inactive (logic 1) state. The
VRST
signal will be driven to a logic 0. V
CC
is still the
power source at this time. When V
CC
drops further to below V
LI
, internal circuitry will switch to the built-
in lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile
states will be retained.
PF
will be driven to a logic 0. The User's Guide has more information on this
topic. The trip points V
CCMIN
and V
PFW
are listed in the electrical specifications.
DS2251T
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.3V to (V
CC
+ 0.5V)
Voltage on V
CC
Relative to Ground
-0.3V to +6.0V
Operating Temperature
-40C to +85C
Storage Temperature
2
-55C to +125C
Soldering Temperature
260C for 10 seconds
1
This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
2
Storage temperature is defined as the temperature of the device when V
CC
=0V and V
LI
=0V. In this state
the contents of SRAM are not battery-backed and are undefined.
DC CHARACTERISTICS (t
A
=0C to70C; V
CC
=5V
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Input Low Voltage
V
IL
-0.3
+0.8
V
1
Input High Voltage
V
IH1
2.0
V
CC
+0.3
V
1
Input High Voltage RST, XTAL1
PROG
V
IH2
3.5
V
CC
+0.3
V
1
Output Low Voltage
@ I
OL
=1.6 mA (Ports 1, 2, 3,
PF
)
V
OL1
0.15
0.45
V
1, 7
Output Low Voltage
@ I
OL
=3.2 mA (Ports 0, ALE,
PSEN
,
BA13-0, BD7-0, R/
W
,
PE
3-4)
V
OL2
0.15
0.45
V
1
Output High Voltage
@ I
OH
= -80
A (Ports 1, 2, 3)
V
OH1
2.4
4.8
V
1
Output High Voltage
@ I
OH
=-400
A (Ports 0, ALE,
PSEN
,
PF
, BA13-0, BD7-0, R/
W
,
PE
3-4)
V
OH2
2.4
4.8
V
1
Input Low Current V
IN
= 0.45V
(Ports 1, 2, 3)
I
IL
-50
A
Transition Current; 1 to 0
V
IN
= 2.0V (Ports 1, 2, 3)
I
TL
-500
A
Input Leakage Current
0.45 < V
IN
< V
CC
(Port 0)
I
IL
10
A
RST Pulldown Resistor
R
RE
40
150
k
VRST
Pullup Resistor
R
VR
4.7
k
PROG
Pullup Resistor
R
PR
40
k
Power-Fail Warning Voltage
V
PFW
4.25
4.37
4.50
V
1
Minimum Operating Voltage
V
CCmin
4.00
4.12
4.25
V
1
Operating Current @ 16 MHz
I
CC
45
mA
2
Idle Mode Current @ 12 MHz
I
IDLE
7.0
mA
3
Stop Mode Current
I
STOP
80
A
4
DS2251T
10 of 20
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Pin Capacitance
C
IN
10
pF
5
Reset Trip Point in Stop Mode
w/BAT=3.0V
w/BAT=3.3V
4.0
4.4
4.25
4.65
V
1
AC CHARACTERISTICS: EXPANDED
BUS MODE TIMING SPECIFICATIONS (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
1
Oscillator Frequency
1/t
CLK
1.0
16 (-16)
MHz
2
ALE Pulse Width
t
ALPW
2t
CLK
-40
ns
3
Address Valid to ALE Low
t
AVALL
t
CLK
-40
ns
4
Address Hold After ALE Low
t
AVAAV
t
CLK
-35
ns
5
ALE Low to Valid Instr. In
@ 12 MHz
@ 16 MHz
t
ALLVI
4t
CLK
-150
4t
CLK
-90
ns
6
ALE Low to
PSEN
Low
t
ALLPSL
t
CLK
-25
ns
7
PSEN
Pulse Width
t
PSPW
3t
CLK
-35
ns
8
PSEN
Low to Valid Instr. In
@ 12 MHz
@ 16 MHz
t
PSLVI
3t
CLK
-150
3t
CLK
-90
ns
ns
9
Input Instr. Hold after
PSEN
Going High
t
PSIV
0
ns
10 Input Instr. Float after
PSEN
Going High
t
PSIX
t
CLK
-20
ns
11 Address Hold after
PSEN
Going High
t
PSAV
t
CLK
-8
ns
12 Address Valid to Valid Instr. In @ 12 MHz
@ 16 MHz
t
AVVI
5t
CLK
-150
5t
CLK
-90
ns
ns
13
PSEN
Low to Address Float
t
PSLAZ
0
ns
14
RD
Pulse Width
t
RDPW
6t
CLK
-100
ns
15
WR
Pulse Width
t
WRPW
6t
CLK
-100
ns
16
RD
Low to Valid Data In
@ 12 MHz
@ 16 MHz
t
RDLDV
5t
CLK
-165
5t
CLK
-105
ns
ns
17 Data Hold after
RD
High
t
RDHDV
0
ns
18 Data Float after
RD
High
t
RDHDZ
2t
CLK
-70
ns
19 ALE Low to Valid Data In
@ 12 MHz
@ 16 MHz
t
ALLVD
8
CLK
-150
8t
CLK
-90
ns
ns
20 Valid Addr. to Valid Data In
@ 12 MHz
@ 16 MHz
t
AVDV
9t
CLK
-165
9t
CLK
-105
ns
ns
21 ALE Low to
RD
or
WR
Low
t
ALLRDL
3t
CLK
-50
3t
CLK
+50
ns
22 Address Valid to
RD
or
WR
Low
t
AVRDL
4t
CLK
-130
ns
23 Data Valid to
WR
Going Low
t
DVWRL
t
CLK
-60
ns
24 Data Valid to
WR
High
@ 12 MHz
t
DVWRH
7t
CLK
-150
ns
DS2251T
11 of 20
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
@ 16 MHz
7t
CLK
-90
ns
25 Data Valid after
WR
High
t
WRHDV
t
CLK
-50
ns
26
RD
Low to Address Float
t
RDLAZ
0
ns
27
RD
or
WR
High to ALE High
t
RDHALH
t
CLK
-40
t
CLK
+50
ns
EXPANDED PROGRAM MEMORY READ CYCLE
DS2251T
12 of 20
EXPANDED DATA MEMORY READ CYCLE
EXPANDED DATA MEMORY WRITE CYCLE
DS2251T
13 of 20
AC CHARACTERISTICS (cont'd)
EXTERNAL CLOCK DRIVE (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
28 External Clock High Time
@ 12 MHz
@ 16 MHz
t
CLKHPW
20
15
ns
ns
29 External Clock Low Time
@ 12 MHz
@ 16 MHz
t
CLKLPW
20
15
ns
ns
30 External Clock Rise Time
@ 12 MHz
@ 16 MHz
t
CLKR
20
15
ns
ns
31 External Clock Fall Time
@ 12 MHz
@ 16 MHz
t
CLKF
20
15
ns
ns
EXTERNAL CLOCK TIMING
AC CHARACTERISTICS (cont'd)
POWER CYCLING TIMING (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
32 Slew Rate from V
CCMIN
to 3.3V
t
F
130
s
33 Crystal Startup Time
t
CSU
(note 6)
34 Power-On Reset Delay
t
POR
21504
t
CLK
DS2251T
14 of 20
POWER CYCLE TIMING
AC CHARACTERISTICS (cont'd)
SERIAL PORT TIMING - MODE 0 (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
35 Serial Port Cycle Time
t
SPCLK
12t
CLK
s
36 Output Data Setup to Rising Clock Edge
t
DOCH
10t
CLK
-133
ns
37 Output Data Hold after Rising Clock Edge
t
CHDO
2t
CLK
-117
ns
38 Clock Rising Edge to Input Data Valid
t
CHDV
10t
CLK
-133
ns
39 Input Data Hold after Rising Clock Edge
t
CHDIV
0
ns
DS2251T
15 of 20
SERIAL PORT TIMING - MODE 0
AC CHARACTERISTICS (cont'd)
PARALLEL PROGRAM LOAD TIMING (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
41 Pulse Width of
PE
3-4
t
CEPW
4t
CLK
-35
ns
45 Byte-wide Address Hold after
PE
3-4 High
During MOVX
t
CEHDA
4t
CLK
-30
ns
46 Delay from Byte-wide Address Valid
PE
3-4
Low During MOVX
t
CELDA
4t
CLK
-35
ns
47 Byte-wide Data Setup to
PE
3-4 High During
MOVX (read)
t
DACEH
1t
CLK
+40
ns
48 Byte-wide Data Hold after
PE
3-4 High
During MOVX (read)
t
CEHDV
10
ns
49 Byte-wide Address Valid to R/
W
Active
During MOVX (write)
t
AVRWL
3t
CLK
-35
ns
50 Delay from R/
W
Low to Valid Data Out
During MOVX (write)
t
RWLDV
20
ns
51 Valid Data Out Hold Time from
PE
3-4 High
t
CEHDV
1t
CLK
-15
ns
52 Valid Data Out Hold Time from R/
W
High
t
RWHDV
0
ns
53 Write Pulse Width (R/
W
Low Time)
t
RWLPW
6t
CLK
-20
ns
DS2251T
16 of 20
BYTE-WIDE BUS TIMING
RPC AC CHARACTERISTICS - DBB READ (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
54
CS
, A
0
Setup to
RD
t
AR
0
ns
55
CS
, A
0
Hold After
RD
t
RA
0
ns
56
RD
Pulse Width
t
RR
160
ns
57
CS
, A
0
to Data Out Delay
t
AD
130
ns
58
RD
to Data Out Delay
t
RD
0
130
ns
59
RD
to Data Float Delay
t
RDZ
85
ns
RPC AC CHARACTERISTICS - DBB READ (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
60
CS
, A
0
Setup to
WR
t
AW
0
ns
61A
CS
, Hold After
WR
t
WA
0
ns
61B A
0
, Hold After
WR
t
WA
20
ns
62
WR
Pulse Width
t
WW
20
ns
63
Data Setup to
WR
t
DW
130
ns
64
Data Hold After
WR
t
WD
20
ns
DS2251T
17 of 20
AC CHARACTERISTICS - DMA (t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
65
DACK
to
WR
or
RD
t
ACC
0
ns
66
RD
or
WR
to
DACK
t
CAC
0
ns
67
DACK
to Data Valid
t
ACD
0
130
ns
68
RD
or
WR
to DRQ Cleared
t
CRQ
110
ns
RPC TIMING MODE 16
AC CHARACTERISTICS -
PROG
(t
A
=0C to70C; V
CC
=5V
10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
69
PROG
Low to Active
t
PRA
48
CLKS
70
PROG
High to Inactive
t
PRI
48
CLKS
DS2251T
18 of 20
RPC TIMING MODE 16 (cont'd)
NOTES:
1.
All voltages are referenced to ground.
2.
Maximum operating I
CC
is measured with all output pins disconnected; XTAL1 driven with t
CLKR
,
t
CLKF
=10 ns, V
IL
= 0.5V; XTAL2 disconnected; RST = PORT0 = V
CC
.
3.
Idle mode I
IDLE
is measured with all output pins disconnected; XTAL1 driven with t
CLKR
, t
CLKF
= 10
ns, V
IL
= 0.5V; XTAL2 disconnected; PORT0 = V
CC
, RST = V
SS
.
4.
Stop mode I
STOP
is measured with all output pins disconnected; PORT0 = V
CC
; XTAL2 not
connected; RST = XTAL1 = V
SS
.
5.
Pin capacitance is measured with a test frequency - 1 MHz, t
A
= 25C.
6.
Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from
the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for a worst case specification on this time.
7.
PF
pin operation is specified with V
BAT
3.0V.
DS2251T
19 of 20
PACKAGE DRAWING
PKG
INCHES
DIM
MIN
MAX
A
4.245
4.255
B
3.979
3.989
C
0.995
1.005
D
0.395
0.405
E
0.245
0.255
F
0.050 BSC
G
0.075
0.085
H
0.245
0.255
I
1.750 BSC
J
0.120
0.130
K
2.120
2.130
L
2.245
2.255
M
0.057
0.067
N
-
0.275
O
-
0.145
P
0.047
0.054
DS2251T
20 of 20
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/13/95 and 08/13/96 version of the DS2251T data
sheet. Please review this summary carefully.
1.
Change V
CC
slew rate definition to reference 3.3V instead of V
LI
.
2.
Add minimum value to PCB thickness.
The following represent the key differences between 08/15/96 and 05/29/97 version of the DS2251T data
sheet. Please review this summary carefully.
1.
PF
signal moved from V
OL2
test specification to V
OL1
. (PCND73001)
The following represent the key differences between 05/28/97 and 11/08/99 version of the DS2251T data
sheet. Please review this summary carefully. (PCN I80903)
1.
Correct Absolute Maximum Ratings to reflect changes to DS5001FP microprocessor.
2.
Add note clarifying that SRAM contents are not defined under storage temperature conditions.
The following represent the key differences between 11/08/99 and 01/18/00 version of the DS2251T data
sheet. Please review this summary carefully.
1.
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