______________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.

General Description

The DS4402 and DS4404 contain two and four I

adjustable current DACs, respectively, that are each
capable of sinking or sourcing current. Each output has
31 sink and 31 source settings that are programmed by
the I

C interface. External resistors set the full-scale

range and step size of each output.

Applications

Power-Supply Adjustment

Power-Supply Margining

Adjustable Current Sink or Source

Features

o Two (DS4402) or Four (DS4404) Current DACs
o Full-Scale Range for Each DAC Determined by

External Resistors

o 31 Settings Each for Sink and Source Modes
o I

C-Compatible Serial Interface

o Two Three-Level Address Pins Allow Nine

Devices on Same I

C Bus

o Low Cost
o Small Package (14-Pin TDFN)
o -40癈 to +85癈 Temperature Range
o 1.7V to 5.5V Operation

DS4402/DS4404

Two/Four-Channel, I

C Adjustable Current DAC

DC/DC

CONVERTER

OUT

SDA

SCL

OUT0

OUT1

GND

FS0

FS1

4.7k

OUT0

FS0

FS1

DS4402

DC/DC

CONVERTER

OUT

OUT1

Typical Operating Circuit

Ordering Information

Rev 0; 4/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.

+Denotes lead-free package.
T&R denotes tape-and-reel package.

PART

TEMP RANGE

PIN-PACKAGE

DS4402N+

-40癈 to +85癈

14 TDFN (3mm x 3mm)

DS4402N+T&R

-40癈 to +85癈

14 TDFN (3mm x 3mm)

DS4404N+

-40癈 to +85癈

14 TDFN (3mm x 3mm)

DS4404N+T&R

-40癈 to +85癈

14 TDFN (3mm x 3mm)

*Purchase of I

C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a

license under the Philips I

C Patent Rights to use these components in an I

C system, provided that the system conforms to the I

Standard Specification as defined by Philips.

TDFN

(3mm x 3mm x 0.8mm)

TOP VIEW

OUT1

SCL

FS3

(N.C.)

FS2

(N.C.)

( ) INDICATES FOR DS4402 ONLY.

OUT3
(N.C.)

OUT2
(N.C.)

SDA

GND

FS1

OUT0

FS0

DS4404/

DS4402

Pin Configuration

DS4402/DS4404

Two/Four-Channel, I

C Adjustable Current DAC

______________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

= -40癈 to +85癈.)

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on V

, SDA, and SCL

Relative to Ground.............................................-0.5V to +6.0V

Voltage Range on A0, A1, FS0, FS1, FS2, FS3,

OUT0, OUT1, OUT2, and OUT3 Relative to
Ground ................-0.5V to (V

+ 0.5V) (Not to exceed 6.0V.)

Operating Temperature Range ...........................-40癈 to +85癈
Storage Temperature Range .............................-55癈 to +125癈
Soldering Temperature .....................................Refer to IPC/JEDEC

J-STD-020 Specification

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

(Note 1)

2.7

5.5

Input Logic 1 (SDA, SCL, A0, A1)

0.7 x

0.3

Input Logic 0 (SDA, SCL, A0, A1)

-0.3

0.3 x

DC ELECTRICAL CHARACTERISTICS

= +2.7V to +5.5V, T

= -40癈 to +85癈.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DS4402

500

Supply Current

= 5.5V

(Note 2)

DS4404

500

礎

Input Leakage (SDA, SCL)

= 5.5V

礎

Output Leakage (SDA)

礎

= 0.4V

Output Current Low (SDA)

= 0.6V

Address Input Resistors

240

Reference Voltage

REF

1.23

OUTPUT CURRENT CHARACTERISTICS

= +2.7V to +5.5V, TA = -40癈 to +85癈.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output Voltage for Sinking Current

OUT:SINK

(Note 3)

0.5

Output Voltage for Sourcing
Current

OUT:SOURCE

(Note 3)

0.5

Full-Scale Sink Output Current

OUT:SINK

(Note 3)

0.5

2.0

Full-Scale Source Output Current

OUT:SOURCE

(Note 3)

-2.0

-0.5

Output-Current Full-Scale
Accuracy

OUT:FS

+ 25癈 , V

C C

= 4.0V ; usi ng i d eal R

r esi stor 2.5

5.0

Output-Current Temperature Drift

OUT:TC

(Note 4)

ppm/癈

DS4402/DS4404

Two/Four-Channel, I

C Adjustable Current DAC

_____________________________________________________________________

Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Supply current specified with all outputs set to zero current setting with all inputs (except A1 and A0, which can be open) driven

to well-defined logic levels. SDA and SCL are connected to V

. Excludes current through R

resistors (I

RFS

). Total current

including I

RFS

is I

+ (2 x I

RFS

Note 3: The output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4: Temperature drift excludes drift caused by external resistor.
Note 5: Differential linearity is defined as the difference between the expected incremental current increase with respect to position

and the actual increase. The expected incremental increase is the full-scale range divided by 31.

Note 6: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.

The expected value is a straight line between the zero and the full-scale values proportional to the setting.

Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I

C standard-mode timing.

Note 8: C

--total capacitance of one bus line in pF.

OUTPUT CURRENT CHARACTERISTICS (continued)

= +2.7V to +5.5V, TA = -40癈 to +85癈.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output-Current Power-Supply
Rejection Ratio

0.33

%/V

Output Leakage Current at Zero
Current Setting

ZERO

-1

礎

Output-Current Differential
Linearity

DNL

(Note 5)

0.5

LSB

Output-Current Integral Linearity

INL

(Note 6)

LSB

C AC ELECTRICAL CHARACTERISTICS

= +2.7V to +5.5V, T

= -40癈 to +85癈.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCL Clock Frequency

SCL

(Note 7)

400

kHz

Bus Free Time Between STOP
and START Conditions

BUF

1.3

祍

Hold Time (Repeated) START
Condition

HD:STA

0.6

祍

Low Period of SCL

LOW

1.3

祍

High Period of SCL

HIGH

0.6

祍

Data Hold Time

DH:DAT

0.9

祍

Data Setup Time

SU:DAT

100

START Setup Time

SU:STA

0.6

祍

SDA and SCL Rise Time

(Note 8)

20 +

0.1C

300

SDA and SCL Fall Time

(Note 8)

20 +

0.1C

300

STOP Setup Time

SU:STO

0.6

祍

SDA and SCL Capacitive Loading

(Note 8)

400

DS4402/DS4404

Two/Four-Channel, I

C Adjustable Current DAC

______________________________________________________________________

FS0

FS1

FS2

FS3

SDA SCL

GND

FS0

FS1

OUT1

OUT0

CURRENT

DAC0

F8h

F9h

SOURCE OR

SINK MODE

FS2

OUT2

FS3

OUT3

CURRENT

DAC3

31-POSITIONS

EACH FOR SINK

AND SOURCE

MODE

FAh

FBh

DS4402/DS4404

DS4404

CURRENT

DAC1

CURRENT

DAC2

C-COMPATIBLE

SERIAL INTERFACE

Figure 1. Functional Diagram

Pin Description

PIN

DS4404

DS4402

NAME

FUNCTION

SDA

C Serial Data. Input/output for I

C data.

SCL

C Serial Clock. Input for I

C clock.

GND

Ground

FS3

FS2

FS1

FS0

Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale
current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (DS4402 has only
two inputs: FS0 and FS1.)

OUT0

OUT1

OUT2

OUT3

Current Output. Sinks or sources the current determined by the I

C interface and the

resistance connected to FSx. (DS4402 has only two outputs: OUT0 and OUT1.)

9, 11

A0, A1

Address Select Inputs. Tri-level inputs (V

, GND, N.C.) determine the I

C slave address.

See the Detailed Description section for the nine available device addresses.

Power Supply

4, 5, 12, 14

N.C.

No Connection

Exposed Pad. Leave floating or connect to GND.

Detailed Description

The DS4402/DS4404 contain two/four I

C adjustable

current sources (Figure 1) that are each capable of
sinking and sourcing current. Each output has 31 sink
and 31 source settings that are programmed through
the I

C interface. The full-scale ranges (and corre-

sponding step sizes) of the outputs are determined by
external resistors that adjust the output currents over a
4:1 range. The formula to determine the external resis-
tor values (R

) for each of the outputs is given by:

Equation 1:

= (V

REF

/ I

) x (31 / 4)

where I

= desired full-scale current

On power-up, the DS4402/DS4404 output zero current.
This is done to prevent it from sinking or sourcing an
incorrect current before the system host controller has
had a chance to modify the device's setting.

As a source for biasing instrumentation or other cir-
cuits, the DS4402/DS4404 provide a simple and inex-
pensive current source with an I

C interface for control.

The adjustable full-scale range allows the application to
get the most out of its 5-bit sink or source resolution.

When used in adjustable power-supply applications
(see the Typical Operating Circuit), the DS4402/DS4404
do not affect the initial power-up supply voltage because
it defaults to providing zero output current on power-up.
As it sources or sinks current into the feedback voltage
node, it changes the amount of output voltage required
by the regulator to reach its steady state operating point.
By using the external resistor to set the output current
range, the devices provide flexibility for adjusting the
impedances of the feedback network or the range over
which the power supply can be controlled or margined.

C Slave Address

The DS4402/DS4404 respond to one of nine I

C slave

addresses determined by the two tri-level address
inputs. The three input states are connected to V

connected to ground, or disconnected. To sense the
disconnected state (Figure 2), the address inputs have
weak internal resistors that pull the pins to mid-supply.

Table 1 lists the slave address determined by the
address input combinations.

DS4402/DS4404

Two/Four-Channel, I

C Adjustable Current DAC

_____________________________________________________________________

Table 1. Slave Addresses

SLAVE ADDRESS

(HEXADECIMAL)

GND

90h

GND

92h

GND

94h

96h

N.C.

GND

98h

N.C.

9Ah

GND

N.C.

9Ch

N.C.

9Eh

N.C.

A0h

ADDRESS

DECODE

Figure 2. I

C Address Inputs

DS4402/DS4404

Memory Organization

To control the DS4402/DS4404's current sources, write
to the memory addresses listed in Table 2.

The format of each output control register is given by:

Where:

Example: I

FS0

= 800礎, and register F8h is written to a

value of 92h. Calculate the value of external resistance
required, and the magnitude of the output current with
this register setting.

= (V

REF

/ 800礎) x (31 / 4) = 11.9k

The MSB of the output register is 1, so the output is
sourcing the value corresponding to position 12h (18
decimal). The magnitude of the output current is equal to:

800礎 x (18 / 31) = 465礎

C Serial Interface Description

C Definitions

The following terminology is commonly used to describe
I

C data transfers:

Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.

Slave Devices: Slave devices send and receive data
at the master's request.

Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.

START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.

STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.

Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition. See Figure 3 for applicable timing.

Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL, plus the
setup and hold time requirements (Figure 3). Data is
shifted into the device during the rising edge of the SCL.

Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (Figure 3) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses, including when it is reading bits from
the slave.

Two/Four-Channel, I

C Adjustable Current DAC

______________________________________________________________________

MSB

LSB

BIT

NAME

FUNCTION

POWER-ON

DEFAULT

Sign Bit

Determines if DAC sources
or sinks current. For sink
S = 0, for source S = 1.

Reserved

Reserved. Both bits read
zero.

00b

Data

5-Bit Data Word Controlling
DAC Output. Setting 00000b
outputs zero current
regardless of the state of the
sign bit.

00000b

Table 2. Memory Addresses

MEMORY ADDRESS

(HEXADECIMAL)

CURRENT SOURCE

F8h

OUT0

F9h

OUT1

FAh*

OUT2*

FBh*

OUT3*

*Only for DS4404.

Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
ninth bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the ninth bit. A device performs a
NACK by transmitting a one during the ninth bit. Timing
for the ACK and NACK is identical to all other bit writes
(Figure 4). An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.

Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant
bit first) plus a 1-bit acknowledgement from the slave to
the master. The 8 bits transmitted by the master are
done according to the bit-write definition, and the
acknowledgement is read using the bit-read definition.

Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave will return control
of SDA to the master.

Slave Address Byte: Each slave on the I

C bus

responds to a slave address byte sent immediately follow-
ing a START condition. The slave address byte contains

the slave address in the most significant 7 bits and the
R/W bit in the least significant bit. The DS4402/DS4404s'
slave address is determined by the state of the A0 and A1
address pins. Table 1 describes the addresses corre-
sponding to the state of A0 and A1.

When the R/W bit is 0 (such as in A0h), the master is
indicating it will write data to the slave. If R/W = 1 (A1h
in this case), the master is indicating it wants to read
from the slave. If an incorrect slave address is written,
the DS4402/DS4404 assume the master is communi-
cating with another I

C device and ignore the commu-

nication until the next START condition is sent.

Memory Address: During an I

C write operation, the

master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.

C Communication

Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave's acknowledgement during all byte-write
operations.

Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.

DS4402/DS4404

Two/Four-Channel, I

C Adjustable Current DAC

_____________________________________________________________________

SDA

SCL

HD:STA

LOW

HIGH

BUF

HD:DAT

SU:DAT

REPEATED

START

SU:STA

HD:STA

SU:STO

STOP

NOTE: TIMING IS REFERENCE TO V

IL(MAX)

AND V

IH(MIN)

START

Figure 3. I

C Timing Diagram

Application Information

Example Calculations

for an Adjustable Power Supply

Using the typical circuit, assuming a typical output volt-
age of 2.0V, a feedback voltage of 0.8V, R1 = 500

and R2 = 333

, to adjust or margin the supply 20%

requires a full-scale current equal to [(0.2 x 2.0V) /
500

= 800礎]. Using Equation 1, R

can be calculat-

ed [R

= (V

REF

/ 800礎) x (31 / 4) = 11.9k

]. The cur-

rent DAC in this configuration allows the output voltage
to be stepped linearly from 1.6V to 2.4V using 63 set-
tings. This corresponds to a resolution of 12.7mV/step.

Power-Supply Feedback Voltage

The feedback voltage for adjustable power supplies
must be between 0.5V and V

- 0.5V for the DS4402/

DS4404 to properly sink/source currents for adjusting
the voltage.

C Reset on Address Change

In addition to defining the I

C slave address, the DS4402/

DS4404 address select inputs have an alternate function.

Changing the address select inputs resets the I

C inter-

face. This function aborts the current transaction and puts
the SDA driver into a high-impedance state. This hard-
ware reset function should never be required because it
is achievable through software, but it does provide an
alternative way of resetting the I

C interface, if needed.

Decoupling

To achieve the best results when using the DS4402/
DS4404, decouple the power supply with a 0.01礔 or
0.1礔 capacitor. Use a high-quality ceramic surface-
mount capacitor if possible. Surface-mount compo-
nents minimize lead inductance, which improves
performance, and ceramic capacitors tend to have
adequate high-frequency response for decoupling
applications.

Layout Considerations

Care should be taken to ensure that traces underneath
the DS4402/DS4404 do not short with the exposed pad.
The exposed pad should be connected to the signal
ground, or can be left floating.

SLAVE

ADDRESS*

START

R/W

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

MSB

LSB

MSB

LSB

MSB

LSB

READ/
WRITE

DATA

STOP

SINGLE BYTE WRITE
-WRITE RESISTOR

F9h TO 00h

SINGLE BYTE READ
-READ RESISTOR F8h

START

REPEATED

START

A1h

MASTER

NACK

STOP

1 0 1 0 0 0 0 0

1 1 1 1 1 0 0 0

F8h

1 0 1 0 0 0 0 1

1 0 1 0 0 0 0 0

1 1 1 1 1 0 0 1

A0h

F9h

STOP

DATA

EXAMPLE I

C TRANSACTIONS (WHEN A0 AND A1 ARE N.C.)

TYPICAL I

C WRITE TRANSACTION

*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1 (SEE TABLE 1).

0 0 0 0 0 0 0 0

A0h

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

Figure 4. I

C Communication Examples

Chip Information

TRANSISTOR COUNT: 10,992

Package Information

For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.

DS4402/DS4404

Two/Four-Channel, I

C Adjustable Current DAC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

� 2006 Maxim Integrated Products

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.

is a registered trademark of Dallas Semiconductor Corporation.

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: DS4404N

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: DS4404N