PIN

FUNCTION

PIN

FUNCTION

+3.2V REF. OUT

NO CONNECTION

UNIPOLAR

NO CONNECTION

ANALOG INPUT

+5V ANALOG SUPPLY

ANALOG GROUND

5V SUPPLY

OFFSET ADJUST

ANALOG GROUND

GAIN ADJUST

COMP. BITS

DIGITAL GROUND

OUTPUT ENABLE

FIFO/DIR

OVERFLOW

FIFO READ

EOC

FSTAT1

+5V DIGITAL SUPPLY

FSTAT2

DIGITAL GROUND

START CONVERT

BIT 1 (MSB)

BIT 16 (LSB)

BIT 1 (MSB)

BIT 15

BIT 2

BIT 14

BIT 3

BIT 13

BIT 4

BIT 12

BIT 5

BIT 11

BIT 6

BIT 10

BIT 7

BIT 9

BIT 8

FEATURES

16-bit resolution

2MHz sampling rate

Functionally complete

No missing codes over full military temperature range

Edge-triggered

±5V supplies, 1.85 Watts

Small, 40-pin, ceramic TDIP

87dB SNR, 88dB THD

Ideal for both time and frequency-domain applications

16-Bit, 2MHz

Sampling A/D Converters

I N N O V A T I O N a n d E X C E L L E N C E

GENERAL DESCRIPTION

The low-cost ADS-932 is a 16-bit, 2MHz sampling A/D
converter. This device accurately samples full-scale input
signals up to Nyquist frequencies with no missing codes. The

dynamic performance of the ADS-932 has been optimized to
achieve a signal-to-noise ratio (SNR) of 87dB and a total
harmonic distortion (THD) of 88dB.

Packaged in a 40-pin TDIP, the functionally complete ADS-932
contains a fast-settling sample-hold amplifier, a subranging
(two-pass) A/D converter, an internal reference, timing/control

logic, and error-correction circuitry. Digital input and output
levels are TTL. The ADS-932 only requires the rising edge of
the start convert pulse to operate.

Requiring only ±5V supplies, the ADS-932 dissipates 1.85
Watts. The device is offered with a bipolar (±2.75V) analog
input range or a unipolar (0 to 5.5V) input range. Models are

available for use in either commercial (0 to +70°C) or military
(55 to +125°C) operating temperature ranges. A proprietary,
auto-calibrating, error-correcting circuit enables the device to

achieve specified performance over the full military
temperature range. Typical applications include medical
imaging, radar, sonar, communications and instrumentation.

INPUT/OUTPUT CONNECTIONS

ADS-932

DATEL, Inc., Mansfield, MA 02048 (USA)

Tel: (508)339-3000, (800)233-2756 Fax: (508)339-6356

E-mail:sales@datel.com

Internet: www.datel.com

Figure 1. ADS-932 Functional Block Diagram

3-STATE

OUTPUT

29 BIT 1 (MSB)
28 BIT 1 (MSB)

27 BIT 2
26 BIT 3
25 BIT 4

24 BIT 5
23 BIT 6
22 BIT 7
21 BIT 8

20 BIT 9
19 BIT 10
18 BIT 11

17 BIT 12
16 BIT 13
15 BIT 14

14 BIT 15
13 BIT 16 (LSB)

TIMING AND

CONTROL LOGIC

GAIN ADJUST 6

+3.2V REF. OUT 1

OFFSET ADJUST 5

EOC 32

ANALOG GROUND 4, 36

DIGITAL GROUND 7, 30

+5V DIGITAL SUPPLY 31

5V SUPPLY 37

+5V ANALOG SUPPLY 38

NO CONNECTION 39, 40

CUSTOM GATE ARRAY

POWER and GROUNDING

2-PASS ANALOG-TO-DIGITAL CONVERTER

S/H

GAIN

ADJUST

CKT.

OFFSET
ADJUST

CKT.

PRECISION

+3.2V REFERENCE

ANALOG INPUT 3

START CONVERT 12

COMP. BITS 35

10 FSTAT1

11 FSTAT2

8 FIFO/DIR
9 FIFO/READ

34 OUTPUT ENABLE

33 OVERFLOW

ADS-932

+25°C

0 to +70°C

55 to +125°C

ANALOG INPUTS

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

UNITS

Input Voltage Ranges

Unipolar

0 to 5.5

Volts

Bipolar

±2.75

Volts

Input Resistance (pin 3)

655

687

685

Input Resistance (pin 2)

418

426

400

Input Capacitance

DIGITAL INPUTS

Logic Levels

Logic "1"

+2.0

Volts

Logic "0"

+0.8

Volts

Logic Loading "1"

+20

µA

Logic Loading "0"

µA

Start Convert Positive Pulse Width

250

STATIC PERFORMANCE

Resolution

Bits

Integral Nonlinearity

±1

±1.5

±2

LSB

Differential Nonlinearity (f

= 10kHz)

0.95

±0.5

+1.0

0.95

±0.5

+1.0

0.95

±0.5

+1.5

LSB

Full Scale Absolute Accuracy

±0.1

±0.3

±0.15

±0.5

±0.8

%FSR

Bipolar Zero Error (Tech Note 2)

±0.1

±0.2

±0.4

±0.5

±0.9

%FSR

Bipolar Offset Error (Tech Note 2)

±0.1

±0.3

±0.2

±0.5

±0.4

±0.9

%FSR

Gain Error (Tech Note 2)

±0.1

±0.3

±0.15

±0.5

±0.9

No Missing Codes (f

= 10kHz)

Bits

DYNAMIC PERFORMANCE

Peak Harmonics (0.5dB)

dc to 500kHz

500kHz to 1MHz

Total Harmonic Distortion (0.5dB)

dc to 500kHz

500kHz to 1MHz

Signal-to-Noise Ratio

(w/o distortion, 0.5dB)

dc to 500kHz

500kHz to 1MHz

Signal-to-Noise Ratio

(& distortion, 0.5dB)

dc to 500kHz

500kHz to 1MHz

Noise

µVrms

Two-Tone Intermodulation

Distortion (f

= 200kHz,

240kHz, f

= 2MHz, 0.5dB)

Input Bandwidth (3dB)

Small Signal (20dB input)

7.8

MHz

Large Signal (0.5dB input)

7.1

MHz

Feedthrough Rejection

= 1MHz)

Slew Rate

±77

V/µs

Aperture Delay Time

Aperture Uncertainty

ps rms

S/H Acquisition Time

( to ±0.001%FSR, 5.5V step)

200

225

200

225

200

225

PARAMETERS

MIN.

TYP.

MAX.

UNITS

Operating Temp. Range, Case

ADS-932MC

+70

°C

ADS-932MM

+125

°C

Thermal Impedance

°C/Watt

Storage Temperature Range

+150

°C

Package Type

40-pin, metal-sealed, ceramic TDIP

Weight

0.56 ounces (16 grams)

ABSOLUTE MAXIMUM RATINGS

PARAMETERS

LIMITS

UNITS

+5V Supply (Pins 31, 38)

0 to +6

Volts

5V Supply (Pin 37)

0 to 6

Volts

Digital Inputs (Pins 8, 9, 12, 34, 35)

0.3 to +V

+0.3

Volts

Analog Input (Pin 3)

Volts

Bipolar

±5

Volts

Unipolar

10 to +5

Volts

Lead Temperature (10 seconds)

+300

°C

PHYSICAL/ENVIRONMENTAL

FUNCTIONAL SPECIFICATIONS

= +25°C, ±V

= ±5V, +V

= +5V, 2MHz sampling rate, and a minimum 3 minute warm-up unless otherwise specified.)

ADS-932

+25°C

0 TO +70°C

55 TO +125°C

DYNAMIC PERFORMANCE

(Cont.)

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

UNITS

Overvoltage Recovery Time

250

500

250

500

250

500

A/D Conversion Rate

MHz

Footnotes:

Effective bits is equal to:

All power supplies must be on before applying a start convert pulse. All

supplies and the clock (START CONVERT) must be present during warm-up

periods. The device must be continuously converting during this time. There is

a slight degradation in performance when operating the device in the unipolar

mode.

When COMP. BITS (pin 35) is low, logic loading "0" will be 350µA.

A 1MHz clock with a positive pulse width is used for all production

testing. See Timing Diagram for more details.
40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns

6.02

(SNR + Distortion) 1.76 + 20 log

Full Scale Amplitude

Actual Input Amplitude

This is the time required before the A/D output data is valid once the analog

input is back within the specified range. This time is only guaranteed if the input

does not exceed ±4.75V (bipolar)

or +2 to 7.5V (unipolar).

The minimum supply voltages of +4.9V and 4.9V for ±V

are required for

55°C operation only. The minimum limits are +4.75V and 4.75V when

operating at +125°C.

TECHNICAL NOTES

1. Obtaining fully specified performance from the ADS-932

requires careful attention to pc-card layout and power supply
decoupling. The device's analog and digital ground systems
are connected to each other internally. For optimal perfor-

mance, tie all ground pins (4, 7, 30 and 36) directly to a
large analog ground plane beneath the package.

Bypass all power supplies and the +3.2V reference output to

ground with 4.7µF tantalum capacitors in parallel with 0.1µF
ceramic capacitors. Locate the bypass capacitors as close
to the unit as possible.

2. The ADS-932 achieves its specified accuracies without the

need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using

the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain calibration hardware,
make adjustments following warm-up. To avoid interaction,

always adjust offset before gain. Tie pins 5 and 6 to
ANALOG GROUND (pin 4) if not using offset and gain adjust
circuits.

3. Pin 35 (COMP. BITS) is used to select the digital output

coding format of the ADS-932 (see Tables 2a and 2b).

When this pin has a TTL logic "0" applied, it complements
all of the ADS-932's digital outputs.

Pin 35 is TTL compatible and can be directly driven with

digital logic in applications requiring dynamic control over its
function. There is an internal pull-up resistor on pin 35
allowing it to be either connected to +5V or left open when a

logic "1" is required.

4. To enable the three-state outputs, connect OUTPUT

ENABLE (pin 34) to a logic "0" (low). To disable, connect pin

34 to a logic "1" (high).

5. Applying a start convert pulse while a conversion is in

progress (EOC = logic "1") will initiate a new and probably

inaccurate conversion cycle. Data from both the interrupted
and subsequent conversions will be invalid.

ANALOG OUTPUT

Internal Reference

Voltage

3.15

+3.2

3.25

3.15

+3.2

3.25

3.15

+3.2

3.25

Volts

Drift

±30

ppm/°C

External Current

DIGITAL OUTPUTS

Logic Levels

Logic "1"

+2.4

Volts

Logic "0"

+0.4

Volts

Logic Loading "1"

Logic Loading "0"

Delay, Falling Edge of Enable to

Output Data Valid

Output Coding

Straight Binary, Complementary Binary, Complementary Offset Binary,

Complementary Two's Complement, Offset Binary, Two's Complement

POWER REQUIREMENTS

Power Supply Ranges

+5V Supply

+4.75

+5.0

+5.25

+4.75

+5.0

+5.25

+4.9

+5.0

+5.25

Volts

5V Supply

4.75

5.0

5.25

4.75

5.0

5.25

4.9

5.0

5.25

Volts

Power Supply Currents

+5V Supply

+225

260

+225

260

+225

260

5V Supply

140

135

140

135

140

135

Power Dissipation

1.85

2.0

1.85

2.0

1.85

2.0

Watts

Power Supply Rejection

±0.07

%FSR/%V

ADS-932

DELAY

PIN

TRANSITION

MIN.

TYP.

MAX.

UNITS

Direct mode to FIFO enabled

FIFO enabled to direct mode

FIFO READ to output data valid

FIFO READ to status update when changing

from <half full (1 word) to empty

FIFO READ to status update when changing

from

half full (8 words) to <half full (7 words)

110

FIFO READ to status update when changing

from full (16 words) to

half full (15 words)

190

Falling edge of EOC to status update when writing

first word into empty FIFO

190

Falling edge of EOC to status update when

changing FIFO from <half full (7 words) to

110

half full (8 words)

Falling edge of EOC to status update when filling

FIFO with 16th word

When the FIFO is initially empty, digital data from the first
conversion (the "oldest" data) appears at the output of the
FIFO immediately after the first conversion has been

completed and remains there until the FIFO is read.

If the output three-state register has been enabled (logic "0"

applied to pin 34), data from the first conversion will appear at
the output of the ADS-932. Attempting to write a 17th word to
a full FIFO will result in that data, and any subsequent

conversion data, being lost.

Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both
equal to "1"), it can be read by dropping the FIFO READ line

(pin 9) to a logic "0" and then applying a series of 15 rising
edges to the read line. Since the first data word is already
present at the FIFO output, the first read command (the first

rising edge applied to FIFO READ) will bring data from the
second conversion to the output. Each subsequent read
command/rising edge brings the next word to the output lines.

After the 15th rising edge brings the 16th data word to the
FIFO output, the subsequent falling edge on READ will update
the status outputs (after a 20ns maximum delay) to FSTAT1 =

0, FSTAT2 = 1 indicating that the FIFO is empty.

If a read command is issued after the FIFO empties, the last
word (the 16th conversion) will remain present at the outputs.

FIFO Reset Feature

At any time, the FIFO can be reset to an empty state by putting

the ADS-932 into its "direct" mode (logic "0" applied to pin 8,
FIFO/DIR) and also applying a logic "0" to the FIFO READ line
(pin 9). The empty status of the FIFO will be indicated by

FSTAT1 going to a "0" and FSTAT2 going to a "1". The status
outputs change 40ns after applying the control signals.

FIFO Status, FSTAT1 and FSTAT2

Monitor the status of the data in the FIFO by reading the two
status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11).

CONTENTS

FSTAT1

FSTAT2

Empty (0 words)

<half full (<8 words)

half-full or more (

8 words)

Full (16 words)

Table 1. FIFO Delays

6. Do not enable/disable or complement the output bits or

read from the FIFO during the conversion process (from the

rising edge of EOC to the falling edge of EOC).

7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the

input voltage exceeds that which produces an output of all

1's or when the input equals or exceeds the voltage that
produces all 0's. When COMP BITS is activated, the above
conditions are reversed.

8. When configuring the ADS-932 for the unipolar mode, Pin 1

(+3.2V REF.) should be connected to Pin 2 (Unipolar)
through a non-inverting op-amp. For precision DC applica-

tions an OP-07 type amplifier is recommended, while AC
applications requiring the lowest level of harmonic distor-
tion should consider the AD9631.

When configuring the ADS-932 for the bipolar mode, Pin 2
(Unipolar) should be physically disconnected from the
surrounding circuitry. This will help prevent noise from

coupling into the A/D.

INTERNAL FIFO OPERATION

The ADS-932 contains an internal, user-initiated, 18-bit, 16-
word FIFO memory. Each word in the FIFO contains the 16

data bits as well as the MSB and overflow bits. Pins 8 (FIFO/
DIR) and 9 (FIFO READ) control the FIFO's operation. The
FIFO's status can be monitored by reading pins 10 (FSTAT1)

and 11 (FSTAT2).

When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is
inserted into the digital data path. When pin 8 has a logic "0"

applied, the FIFO is transparent and the output data goes
directly to the output three-state register (whose operation is
controlled by pin 34 (ENABLE)). Read and write commands to

the FIFO are ignored when the ADS-932 is operated in the
"direct" mode. It takes a maximum of 20ns to switch the FIFO
in or out of the ADS-932's digital data path.

FIFO Write and Read Modes

Once the FIFO has been enabled (pin 8 high), digital data is

automatically written to it, regardless of the status of FIFO
READ (pin 9). Assuming the FIFO is initially empty, it will
accept data (18-bit words) from the next 16 consecutive A/D

conversions. As a precaution, pin 9 (which controls the FIFO's
READ function) should not be low when data is first written to
an empty FIFO.

ADS-932

12) so that the converter is continuously converting.

2. For unipolar or bipolar zero/offset adjust, apply 42µV to the

ANALOG INPUT (pin 3).

3. For bipolar inputs, adjust the offset potentiometer until the

code flickers between 1000 0000 0000 0000 and 0111 1111
1111 1111 with pin 35 tied high (complementary offset

binary) or between 0111 1111 1111 1111 and 1000 0000
0000 0000 with pin 35 tied low (offset binary).
For unipolar inputs, adjust the offset potentiometers until all

output bits are 0's and the LSB flickers between 0 and 1 with
Pin 35 tied high (straight binary) or until all bits are 1's and
the LSB flickers between 0 and 1 with pin 35 tied low

(complementary binary).

4. Two's complement coding requires using BIT 1 (MSB) (pin

29). With pin 35 tied low, adjust the trimpot until the output

code flickers between all 0's and all 1's.

Gain Adjust Procedure

1. Apply +2.749874V to the ANALOG INPUT (pin 3).

2. For bipolar inputs adjust the gain potentiometer until all

output bits are 0's and the LSB flickers between a 1 and 0
with pin 35 tied high (complementary offset binary) or until
all output bits are 1's and the LSB flickers between a 1 and

0 with pin 35 tied low (offset binary).

3. Two's complement coding requires using BIT 1 (MSB)

(pin 29). With pin 35 tied low, adjust the gain trimpot until

the output code flickers equally between 0111 1111 1111
1111 and 0111 1111 1111 1110.

CALIBRATION PROCEDURE

Connect the converter per Figure 2. Any offset/gain
calibration procedures should not be implemented until the

device is fully warmed up. To avoid interaction, adjust offset
before gain. The ranges of adjustment for the circuits in
Figure 2 are guaranteed to compensate for the ADS-932's

initial accuracy errors and may not be able to compensate for
additional system errors.

A/D converters are calibrated by positioning their digital

outputs exactly on the transition point between two adjacent
digital output codes. This is accomplished by connecting
LED's to the digital outputs and performing adjustments until

certain LED's "flicker" equally between on and off. Other
approaches employ digital comparators or microcontrollers to
detect when the outputs change from one code to the next.

For the ADS-932, offset adjusting is normally accomplished
when the analog input is 0 minus ½ LSB (42µV). See Table
2b for the proper bipolar output coding.

Gain adjusting is accomplished when the analog input is at
nominal full scale minus 1½ LSB's (+2.749874V).

Note: Connect pin 5 to ANALOG GROUND (pin 4) for

operation without zero/offset adjustment. Connect pin 6 to pin
4 for operation without gain adjustment.

Zero/Offset Adjust Procedure

1. Apply a train of pulses to the START CONVERT input (pin

Figure 2. Bipolar Connection Diagram

ADS-932

20k

33
32
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13

OVERFLOW
EOC
BIT 1 (MSB)
BIT 1 (MSB)
BIT2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16 (LSB)

ANALOG

GROUND

DIGITAL

GROUND

0.1µF

4.7µF

0.1µF

COMP. BITS

4.7µF

+3.2V

REF. OUT

FIFO READ

7, 30

+5V

DIGITAL

+5V

OFFSET

ADJUST

GAIN

ADJUST

0.1µF

4.7µF

4, 36

0.1µF

4.7µF

20k

+5V

+5V ANALOG

START CONVERT

ANALOG INPUT

ENABLE

FIFO/DIR

FSTAT1

FSTAT2

+5V

UNIPOLAR

CONNECT for UNIPOLAR MODE

6.8µF

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