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General Description
The PEELTM22CV10AZ is a Programmable Electrically
Erasable Logic (PEELTM) device that provides a low power
alternative to ordinary PLDs. The PEELTM22CV10AZ is
available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC
packages (see Figure 19).
A "zero-power" (100A max. I
CC
) standby mode makes the
PEELTM22CV10AZ ideal for power sensitive applications
such as handheld meters, portable communication equip-
ment and laptop computers/ peripherals. EE-reprogramma-
bility provides the convenience of instant reprogramming
for development and a reusable production inventory mini-
mizing the impact of programming changes or errors. EE-
reprogrammability also improves factory testability, thus
ensuring the highest quality possible.
PLCC
SOIC
DIP
1
2
3
4
5
6
7
8
I/CLK
I
I
I
I
I
I
I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
23
22
21
20
19
18
17
9
10
I
I
I/O
I/O
16
15
11
12
I
GND
I/O
I
14
13
TSSOP
The PEELTM22CV10AZ is JEDEC file compatible with stan-
dard 22V10 PLDs. Eight additional configurations per mac-
rocell (a total of 12) are also available by using the "+"
software/programming option (i.e., 22CV10AZ+). The addi-
tional macrocell configurations allow more logic to be put
into every device, potentially reducing the design's compo-
nent count and lowering the power requirements even fur-
ther.
Development and programming support for the
PEELTM22CV10AZ is provided by popular third-party pro-
grammers and development software. ICT also offers free
PLACE development software and a low-cost development
system (PDS-3).
Figure 19 Block Diagram
Features
s
Ultra Low Power Operation
- V
CC
= 5 Volts 10%
- Icc = 10 A (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
- t
PD
= 25ns.
s
CMOS Electrically Erasable Technology
- Superior factory testing
-
Reprogrammable in plastic package
-
Reduces retrofit and development costs
s
Development/Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
s
Architectural Flexibility
-
133 product terms x 44 input AND array
-
Up to 22 inputs and 10 I/O pins
-
12 possible macrocell configurations
-
Synchronous preset, asynchronous clear
-
Independent output enables
-
Programmable clock source and polarity
-
24-pin DIP/SOIC/TSSOP and 28-pin PLCC
s
Application Versatility
-
Replaces random logic
-
Pin and JEDEC compatible with 22V10
-
Ideal for power-sensitive systems
CMOS Programmable Electrically Erasable Logic Device
PEELTM 22CV10AZ -25
Figure 19 Pin Configuration
Commercial/
Industrial
PEELTM 22CV10AZ
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(OPTIONAL)
131
124
130
111
98
83
82
66
49
33
20
21
2
0
132
9
10
34
48
65
121
110
97
I
I
I
I
I
I
I
I/CLK
I
I
I
(2)
(3)
(4)
(5)
(6)
(7)
(9)
(10)
(11)
(12)
(13)
MACRO
CELL
ASYNCHRONOUS CLEAR
(TO ALL MACROCELLS)
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
SYNCHRONOUS PRESET
(TO ALL MACROCELLS)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
(20)
(24)
(27)
(26)
(25)
(23)
(21)
(19)
(18)
(17)
(16)
Figure 21 PEELTM22CV10AZ Logic Array Diagram
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PEELTM 22CV10AZ
Function Description
The implements logic functions as sum-of-products expres-
sions in a programmable-AND/fixed-OR logic array. User-
defined functions are created by programming the connec-
tions of input signals into the array. User-configurable out-
put structures in the form of I/O macrocells further increase
logic flexibility.
Architecture Overview
The architecture is illustrated in the block diagram of Figure
19. Twelve dedicated inputs and 10 I/Os provide up to 22
inputs and 10 outputs for creating logic functions (see Fig-
ure 21). At the core of the device is a programmable electri-
cally-erasable AND array that drives a fixed OR array. With
this structure, the PEELTM22CV10AZ can implement up to
10 sum-of-products logic expressions.
Associated with each of the ten OR functions is an I/O mac-
rocell that can be independently programmed to one of four
different configurations in standard 22V10 mode, or any
one of 12 configurations using the special "Plus" mode. The
programmable macrocells allow each I/O to be used to cre-
ate sequential or combinatorial logic functions of active-
high or active-low polarity, while providing three different
feedback paths into the AND array.
AND/OR Logic Array
The programmable AND array of the PEELTM22CV10AZ
(shown in Figure 21) is formed by input lines intersecting
product terms. The input lines and product terms are used
as follows:
s
44 Input Lines:
24 input lines carry the true and complement of the
signals applied to the 12 input pins
20 additional lines carry the true and complement
values of feedback or input signals from the 10 I/Os
s
133 Product Terms:
120 product terms (arranged in 2 groups of 8, 10, 12,
14, and 16) are used to form sum of product functions
10 output enable terms (one for each I/O)
1 global synchronous preset term
1 global asynchronous clear term
1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
that is connected to both the true and complement of an
input signal will always be FALSE and therefore will not
affect the OR function that it drives. When all the connec-
tions on a product term are opened, a "don't care" state
exists and that term will always be TRUE.
When programming the PEELTM22CV10AZ, the device
programmer first performs a bulk erase to remove the previ-
ous pattern. The erase cycle opens every logical connec-
tion in the array. The device is configured to perform the
user-defined function by programming selected connec-
tions in the AND array. (Note that PEELTM device program-
mers automatically program all of the connections on
unused product terms so that they will have no effect on the
output function).
Variable Product Term Distribution
The PEELTM22CV10AZ provides 120 product terms to
drive the 10 OR functions. These product terms are distrib-
uted among the outputs in groups of 8, 10, 12, 14, and 16
to form logical sums (see Figure 21). This distribution
allows optimum use of the device resources.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides
complete control over the architecture of each output. The
ability to configure each output independently lets you to
tailor the configuration of the PEELTM22CV10AZ to the pre-
cise requirements of your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 20, consists of a D-
type flip-flop and two signal-select multiplexers. The config-
uration of the macrocell is determined by four EEPROM
bits that control the multiplexers. These bits determine the
output polarity, output type (registered or non-registered)
and input-feedback path (bidirectional I/O, combinatorial
feedback). Refer to Table 1. for details. Four of these mac-
rocells duplicate the functionality of the industry-standard
PAL22V10. (See Figure 21 and Table 1.)
Figure 20 Block Diagram of the
PEELTM22CV10A I/O Macrocell
PEELTM 22CV10AZ
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In addition to emulating the four PAL-type output structures
(configurations 3, 4, 9, and 10), The macrocell provides
eight additional configurations. Equivalent circuits for the
twelve macrocell configurations are illustrated in Figure 22.
These structures are accessed by specifying the
PEELTM22CV10A+ or PEELTM22CV10A++ option when
assembling the equations.
Figure 21 Equivalent Circuits for the Four
Configurations of the I/O Macrocell
When creating a PEELTM device design, the desired mac-
rocell configuration is generally specified explicitly in the
design file. When the design is assembled or compiled, the
macrocell configuration bits are defined in the last lines of
the JEDEC programming file.
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type flip-
flop (registered function). The D-type flip-flop latches data
on the rising edge of the clock and is controlled by the glo-
bal preset and clear terms. When the synchronous preset
term is satisfied, the Q output of the register is set HIGH at
the next rising edge of the clock input. Satisfying the asyn-
chronous clear sets Q LOW, regardless of the clock state. If
both terms are satisfied simultaneously, the clear will over-
ride the preset.
Table 1. PEELTM22CV10A Macrocell
Configuration Bits
Configuration
Input/Feedback
Select
Output Select
#
A
B
1
0
0
Register
Feedback
Register
Active Low
2
1
0
Active High
3
0
1
Bi-Directional
I/O
Combinatorial
Active Low
4
Active High
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable out-
put enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is switched into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
When configuring an I/O macrocell to implement a regis-
tered function (configurations 1 and 2 in Figure 21), the Q
output of the flip-flop drives the feedback term. When con-
figuring an I/O macrocell to implement a combinatorial out-
put (configurations 3 and 4 in Figure 21), the feedback term
is taken from the I/O pin. In this case, the pin can be used
as a dedicated input or a bi-directional I/O (Refer also to
Table 1.)
Programmable Clock Options
A unique feature of the PEELTM22CV10AZ is a program-
mable clock multiplexer that allows you to select true or
complement forms of either the input pin or a product-term
clock source. This feature can be accessed by specifying
the PEELTM22CV10A++ option when assembling the equa-
tions.
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PEELTM 22CV10AZ
Table 1. I/O Macrocell Equivalent Circuits
Configuration
Input/Feedback Select
Output Select
#
A
B
C
D
1
0
0
1
0
Bi-directional I/O
Register
Active Low
2
1
0
1
0
Active High
3
0
1
0
0
Combinatorial
Active Low
4
1
1
0
0
Active High
5
0
0
1
1
Combinatorial Feedback
Register
Active Low
6
1
0
1
1
Active High
7
0
1
1
1
Combinatorial
Active Low
8
1
1
1
1
Active High
9
0
0
0
0
Register Feedback
Register
Active Low
10
1
0
0
0
Active High
11
0
1
1
0
Combinatorial
Active Low
12
1
1
1
0
Active High
Figure 22 Equivalent Circuits for the Twelve Configurations of the PEELTM22CV10AZ+ I/O Macrocell
PEELTM 22CV10AZ
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0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
ICC in mA.
Frequency in MHz
22CV10AZ Frequency vs. ICC
Zero Power Feature
The CMOS PEELTM22CV10AZ features "Zero-Power"
standby operation for ultra-low power consumption. With
the "Zero-Power" feature, transition-detection circuitry mon-
itors the inputs, I/Os (including CLK) and feedbacks. If
these signals do not change for a period of time greater
than approximately two t
PD
s, the outputs are latched in their
current state and the device automatically powers down.
When the next signal transition is detected, the device will
"wake up" for active operation until the signals stop switch-
ing long enough to trigger the next power-down.
As a result of the "Zero-Power" feature, significant power
savings can be realized for combinatorial or sequential
operations when the inputs or clock change at a modest
rate (see Figure 23).
Figure 23 Typical ICC vs. Input Clock
Frequency for the 22CV10AZ.
Design Security
The PEELTM22CV10AZ provides a special EEPROM secu-
rity bit that prevents unauthorized reading or copying of
designs programmed into the device. The security bit is set
by the PLD programmer, either at the conclusion of the pro-
gramming cycle or as a separate step, after the device has
been programmed. Once the security bit is set it is impossi-
ble to verify (read) or program the PEELTM until the entire
device has first been erased with the bulk-erase function.
Signature Word
The signature word feature allows a 64-bit code to be pro-
grammed into the PEELTM22CV10AZ if the
PEELTM22CV10AZ+ software option is used. The code can
be read back even after the security bit has been set. The
signature word can be used to identify the pattern pro-
grammed into the device or to record the design revision,
etc.
Programming Support
ICT's JEDEC file translator allows easy conversion of exist-
ing 24 pin PLD designs to the PEELTM22CV10AZ, without
the need for redesign. ICT supports a broad range of popu-
lar third party design entry systems, including Data I/O
Synario and Abel, Logical Devices CUPL and others. ICT
also offers (for free) its proprietary PLACE software, an
easy-to-use entry level PC-based software development
system.
Programming support includes all the popular third party
programmers; Data I/O, Logical Devices, and numerous
others. ICT also provides a low cost development program-
mer system, the PDS-3.
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PEELTM 22CV10AZ
Table 1. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Rating
Unit
V
CC
Supply Voltage
Relative to Ground
-0.5 to + 7.0
V
V
I
, V
O
Voltage Applied to Any Pin
2
Relative to Ground
1
-0.5 to V
CC
+ 0.6
V
I
O
Output Current
Per Pin (I
OL
, I
OH
)
25
mA
T
ST
Storage Temperature
-65 to +150
C
T
LT
Lead Temperature
Soldering 10 Seconds
+300
C
Table 2. Operating Range
Symbol
Parameter
Conditions
Min
Max
Unit
Vcc
Supply Voltage
Commercial
4.75
5.25
V
Industrial
4.5
5.5
V
T
A
Ambient Temperature
Commercial
0
+70
C
Industrial
-40
+85
C
T
R
Clock Rise Time
See Note 3.
20
ns
T
F
Clock Fall TIme
See Note 3.
20
ns
T
RVCC
V
CC
Rise Time
See Note 3.
250
ms
Table 3. D.C. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
V
OH
Output HIGH Voltage - TTL
V
CC
= Min, I
OH
= -4.0 mA
2.4
V
V
OHC
Output HIGH Voltage - CMOS
V
CC
= Min, I
OH
= -10.0 A
V
CC
- 0.3
V
V
OL
Output LOW Voltage - TTL
V
CC
= Min, I
OL
= 16.0 mA
0.5
V
V
OLC
Output LOW Voltage - CMOS
V
CC
= Min, I
OL
= 10.0 A
0.15
V
V
IH
Input HIGH Voltage
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
-0.3
0.8
V
I
IL
Input and I/O Leakage Current
V
CC
= Max, GND
V
IN
V
CC
, I/O = High Z
10
A
I
SC
Output Short Circuit Current
V
CC
= Max, V
O
= 0.5V, TA = 25C
-30
-135
mA
I
CCS
V
CC
Current, Standby
VIN = 0V or V
CC
, All Outputs disabled
4
10 (typ)
100
A
I
CC
10
V
CC
Current, f=1MHz
VIN = 0V or V
CC
, All Outputs disabled
4
2 (typ)
5
mA
C
IN
7
Input Capacitance
TA = 25C, V
CC
= 5.0V @ f = 1 MHz
6
pF
C
OUT
7
Output Capacitance
12
pF
Over the operating range (Unless otherwise specified)
This device has been designed and tested for the specified
operating ranges. Proper operation outside of these levels
is not guaranteed. Exposure to absolute maximum ratings
may cause permanent damage.
PEELTM 22CV10AZ
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Switching Waveforms
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for
periods less than 20 ns.
2. V
I
and V
O
are not specified for program/verify operation.
3. Test Points for Clock and VCC in t
R
and t
F
are referenced at the 10%
and 90% levels.
4. I/O pins are 0V and V
CC
.
5. "Input" refers to an input pin signal.
6. t
OE
is measured from input transition to V
REF
0.1V, T
OD
is measured
from input transition to V
OH
-0.1V or V
OL
+0.1V; V
REF
=V
L.
7. Capacitances are tested on a sample basis.
Table 10.
Symbol
Parameter
-25
Units
Min
Max
t
PD
Input
5
to non-registered output
25
ns
t
OE
Input
5
to output enable
6
25
ns
t
OD
Input
5
to output disable
6
25
ns
t
CO1
Clock to Output
15
ns
t
CO2
Clock to comb. output delay via internal registered feedback
35
ns
t
CF
Clock to Feedback
9
ns
t
SC
Input
5
or feedback setup to clock
15
ns
t
HC
Input
5
hold after clock
0
ns
t
CL
, t
CH
Clock low time, clock high time
8
13
ns
t
CP
Min clock period Ext (t
SC
+ t
CO1
)
30
ns
f
MAX1
Internal feedback (1/t
SC
+t
CF
)
11
41.6
MHz
f
MAX2
External Feedback (1/t
CP
)
11
33.3
MHz
f
MAX3
No Feedback (1/t
CL
+t
CH
)
11
38.4
MHz
t
AW
Asynchronous Reset Pulse Width
25
ns
t
AP
Input to Asynchronous Reset
25
ns
t
AR
Asynchronous Reset recovery time
25
ns
t
RESET
Power-on reset time for registers in clear state
12
5
s
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
8. Test conditions assume: signal transition times of 3ns or less from the
10% and 90% points, timing reference levels of 1.5V (Unless otherwise
specified).
9. Test one output at a time for a duration of less than 1 second.
10. I
CC
for a typical application: This parameter is tested with the device
programmed as a 10-bit Counter.
11. Parameters are not 100% tested. Specifications are based on initial
characterization and are tested after any design process modification that
might affect operational frequency.
12. All inputs at GND.
Over the operating range
8
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PEELTM 22CV10AZ
PEELTM Device and Array Test Loads
Part Number
Technology
R1
R2
R
L
V
L
C
L
CMOS
480k
480k
228k
2.375V
33 pF
TTL
235
159
95
2.02V
33 pF
Part Number
Speed
Temperature
Package
PEEL22CV10AZP-25
25ns
Commercial
24-pin Plastic DIP
PEEL22CV10AZJ-25
25ns
Commercial
28-pin PLCC
PEEL22CV10AZS-25
25ns
Commercial
24-pin SOIC
PEEL22CV10AZT-25
25ns
Commercial
24-pin TSSOP
PEEL22CV10AZPI-25
25ns
Industrial
24-pin Plastic DIP
PEEL22CV10AZJI-25
25ns
Industrial
28-pin PLCC
PEEL22CV10AZSI-25
25ns
Industrial
24-pin SOIC
PEEL22CV10AZTI-25
25ns
Industrial
24-pin TSSOP
Output
C
L
R2
R1
5 V
Standard
Load
Output
C
L
R
L
V
L
Thevenin
Equivalent
Device
PEELTM 22CV10AZ
Suffix
PI-25
Package
P = 24-pin Plastic 300mil DIP
J = 28-pin Plastic (J) Leaded Chip Carrier (PLCC)
S = 24-pin SOIC 300 mil Gullwing
T = 24-pin TSSOP 170 mil
Speed
25 = 25ns tpd
Temperature Range
(Blank) = Commercial 0 to +70C
I = Industrial -40 to +85C
Ordering Information
PEELTM 22CV10AZ
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