DESCRIPTION:
The LP-StackTM series is a family of interchangeable memory devices. The 256 Megabit Double Data Rate Synchronous DRAM is a
member of this family which utilizes the new and innovative space saving TSOP stacking technology. The devices are constructed
with two 16 Meg x 8 DDR SDRAM's.
This 256 Megabit based LP-StackTM module
DPDD16MX16TSBY5, based on 128 Megabit devices, has
been designed to fit in the same footprint as the 16 Meg x 8
DDR SDRAM TSOP monolithic and 512 Megabit SDRAM
based family of LP-StackTM. This allows for system upgrade
without electrical or mechanical redesign. Providing an
immediate and low cost memory solution.
FEATURES:
Configuration Available:
16 Meg x 16 bit (2 Banks of 4 Meg x 8 bits x 4)
Clock Frequency: 100, 125, 133, 143 MHz
2.5 Volt DQ Supply
JEDEC Standard SSTL_2 Interface for all Inputs/Outputs
Four Bank Operation
Programmable Burst Type:
Burst Length and Read Latency
Refresh: 4096 Cycles/64ms
Refresh Types: Auto and Self
JEDEC Approved Footprint and Pinout
Package: 66-Pin Leadless TSOP Stack
A0-A11
Row Address:
A0-A11
Column Address: A0-A9
BA0,BA1
Bank Select Address
A10/AP
Auto Precharge
DQ0-DQ15
Data In/Data Out
CAS
Column Address Strobes
CS
Chip Selects
RAS
Row Address Strobe
WE
Data Write Enables
CK, CK
Differential Clock Inputs
CKE0, CKE1
Clock Enables
DQS0, DQS1
Data Strode
DM0, DM1
Data Mask
V
DD
Power Supply (+2.5V)
Vss
Ground
V
DDQ
DQ Power Supply (+2.5V)
Vss
Q
DQ Ground
V
REF
Reference Voltage for inputs
N.C.
No Connect
NU
Not Used
30A245-00
REV. B 8/01
This document contains information on a product under consideration for development at DPAC Technologies Corp.
DPAC reserves the right to change or discontinue information on this product without prior notice.
256 Megabit CMOS DDR SDRAM
DPDD16MX16TSBY5
A
D
V
A
N
C
E
D
I
NFO
RM
A
T
I
O
N
CAS
CS
WE
DQ0-DQ7
CKE0
16
Mx8 DDR S
DRA
M
DM0
CK
RAS
CKE1
CK
A0-A11
VREF
DQS1
DQS0
16
Mx8 DDR S
DRA
M
DM1
1
PIN NAMES
FUNCTIONAL BLOCK DIAGRAM
ADVAN C E D C O M P O N E NTS PAC K AG I N G
1
(TOP VIEW)
60
DQ14
VDD
1
2
54
DQ12
VDDQ
3
53
DQ8
4
52
VSSQ
DQ1
5
51
DQS0
VSSQ
6
50
DM1
DQ9
7
49
VREF
8
48
VSS
VDDQ
9
47
DQ10
10
46
CK
DQ3
11
45
CK
VSSQ
12
44
CKE0
DQ11
13
43
CKE1
N.C.
14
42
N.C.
VDDQ
15
41
A11
N.C.
16
40
A9
N.C.
17
39
A8
VDD
18
38
A7
N.C.
19
37
A6
N.C.
20
36
A5
WE
21
35
A4
CAS
22
34
VSS
RAS
23
59
DQ5
CS
24
57
VSSQ
N.C.
25
57
DQ13
BA0
26
56
DQ4
BA1
27
55
VDDQ
DQ2
DQ0
DM0
DQS1
33
VDD
32
A3
31
A2
30
A1
29
A0
28
A10/AP
VDDQ
61
DQ6
62
DQ15
63
VSSQ
64
DQ7
65
VSS
66
PIN-OUT DIAGRAM
20
15
DP
XX
-
CAS
DOUBLE DATA RATE SYNCHRONOUS DRAM
PREFIX
CAS LATENCY 1.5
CAS LATENCY 2.0
DD
16M
X
16
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
T
128 MEGABIT BASED
STACKABLE TSOP
MANUFACTURER CODE*
XX
-
MFR ID
SUPPLIER
DP
SUPPLIER CODE*
I/O TYPE
S
SSTL INPUTS/OUTPUTS
WIDTH
DEVICE
B
x8 MEMORY BASED
CAS LATENCY 2.5
25
10
10ns (100MHz)
8ns (125MHz)
7.5ns (133MHz)
75
08
CYCLE
XX
TIME
LATENCY
7ns (143MHz)
07
PART NUMBER DESCRIPTION
30A245-00
REV. B 8/01
2
1
.015 [.18]
.0256 [.65]
.102 MAX
PIN 1
INDEX
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
.502.008
.885.010
.427 [10.85]
.417 [10.59]
.527 [13.39]
.517 [13.13]
.0256 [.65] BSC
.016 [.41]
Standard TSOP pad layout is acceptable, however, when possible, the
following pad layout is recommended for optimal manufacture and
inspection. See Application Note 53A001-00 for further information.
[12.75.20]
[22.48.25]
[2.59 MAX]
.819 [20.80] BSC
.020 [.51]
TYP
TYP
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2001 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS StackTM are trademarks of DPAC Technologies Corp.
DPDD16MX16TSBY5
256 Megabit CMOS DDR SDRAM
A
D
V
A
N
C
E
D
I
NFO
RM
A
T
I
O
N
MECHANICAL DRAWING
* Contact your sales representative for manufacturer and supplier codes.
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