PIN NAMES
A0-A12
Row Address:
A0 - A12
Column Address:
A0 - A9
BA0,BA1
Bank Select Address
A10/AP
Auto Precharge
DQ0-DQ15
Data In/Data Out
CAS
Column Address Strobe
CS
Chip Select
RAS
Row Address Strobe
WE
Data Write Enable
CK, CK
Differential Clock Inputs
CKE
Clock Enable
UDQS0, UDQS1 Upper Data Strobe
LDQS0,LDQS1
Lower Data Strobe
UDM0, UDM1
Upper Data Mask
LDM0, LDM1
Lower Data Mask
V
DD
Power Supply (+2.5V)
Vss
Ground
V
DDQ
DQ Power Supply (+2.5V)
Vss
Q
DQ Ground
V
REF
Reference Voltage for inputs
N.C.
No Connect
DESCRIPTION:
The Memory StackTM series is a family of interchangeable
memory modules. The 512 Megabit Double Data Rate
Synchronous DRAM module is a member of this family
which utilizes the space saving LP-StackTM TSOP stacking
technology. The devices are constructed with two 16 Meg x 16
DDR SDRAMs.
This 256 Megabit based LP-StackTM module
DPDD16MX32WCD5, has been designed to fit in a footprint
similar to the 16 Meg x 16 DDR SDRAM TSOPII monolithic
with minimal width increase to accommodate an additional
row of interface pads.
FEATURES:
Configuration:
16M x 32 (2 Banks of 4 Meg x 16 bits x 4 banks)
IPC-A-610 Manufacturing Standards
Package: 87-Pin Dual Row TSOP Stack
The following features are not affected by LP-Stack and are
provided as reference only. Refer to memory OEM device
specification for details.
Clock Frequency is determined by OEM memory
device used.
2.5 Volt DQ Supply
JEDEC Standard SSTL_2 Interface for all Inputs/Outputs
Four Bank Operation
Programmable Burst Type:
Burst Length and Read Latency
Refresh: Refer to memory OEM specifications
Auto and Self Refresh
This document contains information on a product under consideration for development at DPAC Technologies Corp.
DPAC reserves the right to change or discontinue information on this product without prior notice.
512 Megabit CMOS DDR SDRAM
DPDD16MX32WCD5
A
D
V
A
N
C
E
D
I
NFO
RM
A
T
I
O
N
1
ADVAN C E D C O M P O N E NTS PAC K AG I N G
30A256-00
REV. A 7/02
MECHANICAL DRAWING
LDM0
CAS
WE
DQ0-DQ15
CS
RAS
CK
UDQS0
CK
A0-A12,BA0,BA1
VREF
CKE
LDQS0
(4 Meg x 16 B
i
ts x 4 B
anks)
256 Mb DDR SDRAM
UDM0
UDM1
LDQS1
UDQS1
LDM1
(4 Meg x 16 B
i
ts x 4 B
anks)
256 Mb DDR SDRAM
DQ16-DQ31
M0
M1
PINOUT DIAGRAM
DQ12
DQ3
60
7
WE
A10/AP
A0
A1
A2
A3
VDD
33
32
31
30
29
28
CAS
RAS
CS
BA0
BA1
N.C.
27
26
25
24
23
22
21
DQ23
14
VDDQ
N.C.
LDQS0
LDQS1
VDD
LDM
20
19
18
17
16
15
VDDQ
VSSQ
DQ4
DQ5
DQ6
DQ7
13
12
11
10
9
8
CK
34
35
36
37
38
39
A8
A7
A6
A5
A4
VSS
40
41
42
43
44
45
46
CK
CKE0
N.C.
A11
A9
A12
DQ24
53
47
48
49
50
51
52
VSSQ
UDQS0
N.C.
VREF
VSS
UDM0
54
55
56
57
58
59
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VDDQ
VSSQ
VDD
DQ0
DQ1
DQ2
6
5
4
3
2
1
1
61
62
63
64
65
66
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
N.C.
VSS
UDM1
DQ26
DQ25
UDQS1
DQ31
DQ29
DQ28
DQ27
DQ30
78
77
79
82
81
80
83
86
85
84
87
67
DQ16
VDD
LDM1
N.C. 75
76
74
DQ21
DQ22
DQ18
DQ19
DQ20
DQ17
72
73
71
68
69
70
* Contact your sales representative for supplier and manufacturer codes.
30A256-00
REV. A 7/02
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2002 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS StackTM are trademarks of DPAC Technologies Corp.
DPDD16MX32WCD5
512 Megabit CMOS DDR SDRAM
A
D
V
A
N
C
E
D
I
NFO
RM
A
T
I
O
N
MECHANICAL DRAWING
.558 .006 [14.170.15]
PIN 1
INDEX
1
.531 .006 [13.490.15]
.497 .006 [12.620.15]
.016 [.41]
.102 [2.59] MAX.
.082 [2.08] MIN.
LEAD HEIGHT
TOE TO TOE
.005 +.003
-.001
[
.13+0.08
-0.03
]
SIDE VIEW
.885.006
[22.48.15]
TOP VIEW
.870.003
[22.10.08]
.463.008
[11.76.20]
BOTTOM VIEW
.015 [.38] TYP
21X
.013 [.33]
.0256 [.65]
BSC
BSC
1
END VIEW
INCH [mm]
MECHANICAL DRAWING
20
15
DP
XX
-
CAS
DOUBLE DATA RATE SYNCHRONOUS DRAM
PREFIX
CAS LATENCY 1.5
CAS LATENCY 2.0
DD
16M
X
32
D5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
W
256 MEGABIT BASED
DUAL ROW TSOP STACK
MANUFACTURER CODE *
XX
-
MFR ID
SUPPLIER
DP
SUPPLIER CODE *
WIDTH
DEVICE
C
x16 MEMORY BASED
CAS LATENCY 2.5
25
CYCLE
XX
TIME
LATENCY
60
6ns (166MHz)
7ns (143MHz)
7.5ns (133MHz)
8ns (125MHz)
10ns (100MHz)
10
75
08
70
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