PIN NAMES
A0-A12
Row Address:
A0 - A12
Column Address:
A0 - A9
BA0,BA1
Bank Select Address
A10/AP
Auto Precharge
DQ0-DQ15
Data In/Data Out
CAS
Column Address Strobe
CS0, CS1
Chip Selects
RAS
Row Address Strobe
WE
Data Write Enable
CK, CK
Differential Clock Inputs
CKE0, CKE1
Clock Enables
UDQS, LDQS
Data Strobe
UDM, LDM
Data Mask
V
DD
Power Supply
Vss
Ground
V
DDQ
DQ Power Supply
Vss
Q
DQ Ground
V
REF
SSTL_2 Reference Voltage
NC
No Connect
DNU
Do Not Use
This document contains information on a product that is currently released to production at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
512 Megabit CMOS DDR SDRAM
DPDD32MX16WSCY5
1
ADVAN C E D C O M P O N E NTS PAC K AG I N G
30A246-00
REV. E 2/03
DESCRIPTION:
The Memory StackTM series is a family of interchangeable memory devices. The 512 Mb, CMOS DDR Synchronous DRAM,
assembly utilizes the space saving LP-StackTM technology to increase memory density. This stack is constructed with two
256Mb (16M x 16) DDR SDRAMs.
This 512 Mb LP-StackTM has been designed to fit in the same
footprint as the 256Mb (16M x 16) DDR SDRAM TSOPII
monolithic. This allows system upgrade without electrical or
mechanical redesign, providing an alternative and low cost
memory solution.
FEATURES:
Electrical characteristics meet semiconductor
manufacturers' datasheets
Memory organization:
(2) 256Mb memory devices. Each device arranged
as 16M x 16 bits (4M x 16 bits x 4 banks)
Memory stack organization:
32M x 16 bits (8M x 16 bits x 4 banks)
JEDEC approved, 2 Rank stack pinout and footprint
(with 2 CSs and 2 CKEs)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 66-Pin TSOPII stack
FUNCTIONAL BLOCK DIAGRAM
UDM/LDM
CAS
WE
DQ0-DQ15
CS0
RAS
CK
UDQS/LDQS
CS1
CK
A0-A12
VREF
CKE1
CKE0
BA0-BA1
(4M x 16 bits x 4 banks)
256 Mb DDR SDRAM
(4M x 16 bits x 4 banks)
PINOUT DIAGRAM
1
(TOP VIEW)
60
DQ12
VDD
1
2
54
DQ8
VDDQ
3
53
DQ1
4
52
VSSQ
DQ2
5
51
UDQS
VSSQ
6
50
DNU
DQ3
7
49
VREF
8
48
VSS
VDDQ
9
47
DQ5
10
46
CK
DQ6
11
45
CK
VSSQ
12
44
CKE0
DQ7
13
43
CKE1
NC
14
42
A12
VDDQ
15
41
A11
LDQS
16
40
A9
NC
17
39
A8
VDD
18
38
A7
DNU
19
37
A6
LDM
20
36
A5
WE
21
35
A4
CAS
22
34
VSS
RAS
23
59
DQ11
CS0
24
58
VSSQ
CS1
25
57
DQ10
BA0
26
56
DQ9
BA1
27
55
VDDQ
DQ4
DQ0
UDM
NC
33
VDD
32
A3
31
A2
30
A1
29
A0
28
A10/AP
VDDQ
61
DQ13
62
DQ14
63
VSSQ
64
DQ15
65
VSS
66
30A246-00
REV. E 2/03
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2003 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, LP-StackTM, CS-StackTM are trademarks of DPAC Technologies Corp.
DPDD32MX16WSCY5
512 Megabit CMOS DDR SDRAM
MECHANICAL DIAGRAM
1
.015 [.18]
.0256 [.65]
.102 MAX [2.59 MAX]
PIN 1
INDEX
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
.502.008
.891 MAX.
[12.75.20]
[22.63 MAX.]
TYP
TYP
END VIEWDETAIL
.463 [11.76] TYP
Lead Toe-to-Toe per device datasheet
Inch [mm]
.004 [.10] from seating plane
COPLANARITY:
ORDERING INFORMATION
DP
X
-
MFR
DOUBLE DATA RATE SYNCHRONOUS DRAM
PREFIX
DD 32M
X
16
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
W
256 MEGABIT BASED
STACKABLE TSOP
MANUFACTURER CODE *
XX
-
MFR ID
SUPPLIER
DP
SUPPLIER CODE *
I/O TYPE
S
SSTL INPUTS/OUTPUTS
WIDTH
DEVICE
C
x16 MEMORY BASED
CLOCK
XX
SPEED
REV
REVISION NOT SPECIFIED
MANUFACTURER DIE REVISION
BLANK
X
XX
LATENCY
CAS
CAS LATENCY
CLOCK SPEED (ns)
* Contact your sales representative for supplier and manufacturer codes.
NOTES:
1. AC Parameters of base memory are unchanged from device manufacturers' specifications.
2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
3. For assembly and inspection procedures, refer to application note 53A001-00.
4. Maximum reflow temperature recommendation is 215C.
PDF 
ZIP