Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a "controlled document". Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
2001 Elantec Semiconductor, Inc.
E
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General Description
The EL5485C and EL5486C comparators are designed for operation
in single supply and dual supply applications with 5V to 12V between
V
S
+ and V
S
-. For single supplies, the inputs can operate from 0.1V
below ground for use in ground sensing applications.
The output side of the comparators can be supplied from a single sup-
ply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5485C and EL5486C can be used to hold the
comparator output value by applying a low logic level to the pin.
The EL5485C is available in the 16-pin SO package and the EL5486C
in the 24-pin QSOP package. Both are specified for operation over the
full -40C to +85C temperature range. Also available are single
(EL5185C), dual (EL5285C), and window comparator (EL5287C)
versions.
Pin Configurations
1
2
3
4
16
15
14
13
5
6
7
12
11
10
8
9
EL5485CS
(16-Pin SO)
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
EL5486CU
(24-Pin QSOP)
- +
-
+
- +
-
+
INA-
INA+
GND
OUTA
OUTB
VS-
INB+
INB-
IND-
IND+
VS+
OUTD
OUTC
VSD
INC+
INC-
- +
-
+
- +
-
+
LATCHA
OUTA
OUTB
LATCHB
VS-
NC
INB+
INB-
LATCHD
OUTD
OUTC
LATCHC
VSD
NC
INC+
INC-
INA-
INA+
NC
GND
IND-
IND+
NC
VS+
Features
4ns typ. propagation delay
5V to 12V input supply
+2.7V to +5V output supply
True-to-ground input
Rail-to-rail outputs
Separate analog and digital
supplies
Active low latch
Single (EL5185C) available
Dual (EL5285C) available
Window available (EL5287C)
Pin-compatible 8ns family
available (EL5x81C, EL5283C &
EL5482C)
Applications
Threshold detection
High speed sampling circuits
High speed triggers
Line receivers
PWM circuits
High speed V/F converters
Ordering Information
Part No
Package
Tape & Reel
Outline #
EL5485CS
16-Pin SO
-
MDP0027
EL5485CS-T7
16-Pin SO
7"
MDP0027
EL5485CS-T13
16-Pin SO
13"
MDP0027
EL5486CU
24-Pin QSOP
-
MDP0040
EL5486CU-T13
24-Pin QSOP
13"
MDP0040
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
S
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p
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7
,
2
0
0
1
2
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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Absolute Maximum Ratings
(T
A
= 25C)
Absolute maximum ratings are those values beyond which the device
could be permanently damaged. Absolute maximum ratings are stress
ratings only and functional device operation is not implied
Analog Supply Voltage (V
S
+ to V
S
-)
+12.6V
Digital Supply Voltage (V
SD
to GND)
+7V
Differential Input Voltage
[(V
S
-) -0.2V] to [(V
S
+) +0.2V]
Common-Mode Input Voltage
[(V
S
-) -0.2V] to [(V
S
+) +0.2V]
Latch Input Voltage
-0.2V to [(V
SD
) +0.2V]
Storage Temperature Range
-65C to +150C
Ambient operating Temperature
-40C to +85C
Operating Junction Temperature
125C
Power Dissipation
TBDmW
ESD Voltage
2kV
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
.
Electrical Characteristics
V
S
= 5V, V
SD
= 5V, R
L
= 2.3k
, C
L
= 15pF, T
A
= 25C, unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
Unit
Input
V
OS
Input Offset Voltage
V
CM
= 0V, V
O
= 2.5V
1
4
mV
I
B
Input Bias Current
-10
-5
A
C
IN
Input Capacitance
5
pF
I
OS
Input Offset Current
V
CM
= 0V, V
O
= 2.5V
-2.5
0.5
2.5
A
V
CM
Input Voltage Range
(V
S
-) - 0.1
(V
S
+) - 2.25
V
CMRR
Common-mode Rejection Ratio
-5V < V
CM
< +2.75V, V
O
= 2.5V
-65
-90
dB
Output
V
OH
Output High Voltage
V
IN
> 250mV
V
SD
- 0.6
V
SD
- 0.4
V
V
OL
Output Low Voltage
V
IN
> 2 50mV
GND + 0.25
GND + 0.5
V
Dynamic Performance
t
pd
+
Latch Disable to High Delay
V
IN
= 1V
P-P
, V
OD
= 50mV
4
6
ns
t
pd
-
Latch Disable to Low Delay
V
IN
= 1V
P-P
, V
OD
= 50mV
4
6
ns
Supply
I
S
+
Positive Analog Supply Current
(per comparator)
12
13
mA
I
S
-
Negative Analog Supply Current
(per comparator)
7.5
8.5
mA
I
SD
Digital Supply Current
(per comparator) All inputs high
5.5
6.5
mA
(per comparator) All inputs low
0.9
1.2
mA
PSRR
Power Supply Rejection Ratio
-60
-80
dB
Latch
V
LH
Latch Input Voltage High
2.0
V
V
LL
Latch Input Voltage Low
0.8
V
I
LH
Latch Input Current High
V
LH
= 3.0V
-30
-18
A
I
LL
Latch Input Current Low
V
LL
= 0.3V
-30
-24
A
t
d
+
Positive Going Delay Time
V
OD
= 5mV, C
L
= 15pF, I
O
= 2mA
4
ns
t
d
-
Negative Going Delay Time
V
OD
= 5mV, C
L
= 15pF, I
O
= 2mA
4
ns
t
s
Minimum Setup Time
2
ns
t
h
Minimum Hold Time
1
ns
t
pw
(D)
Minimum Latch Disable Pulse Width
5
ns
3
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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Typical Performance Curves
Supply Current vs Supply Voltage
(per comparator)
0
1
2
3
4
5
6
10
8
6
4
2
0
V
S
(V)
I
S
(
m
A
)
I
S
+
I
S
-
V
IN
=50mV
R
L
=2.2k
Offset Voltage vs Temperature
-50
-30
10
30
50
70
90
3
2.5
1.5
1
0.5
0
Temperature (C)
V
O
S
(
m
V
)
2
-10
Output High Voltage vs Temperature
-50
-30
10
30
50
70
90
4.832
4.83
4.826
4.822
4.82
4.818
Temperature (C)
V
O
H
(
V
)
4.828
4.824
-10
Input Bias Current vs Temperature
-50
-30
30
50
90
8
7
3
2
1
0
Temperature (C)
I
B
(
A
)
5
-10
10
70
6
4
Propagation Delay vs Overdrive
V
IN
=5V
STEP
0.2
0.6
1
1.4
1.8
2.2
2.6
7.8
7.4
7
6.8
6.6
6.4
V
OD
(V)
D
e
l
a
y
T
i
m
e
(
n
s
)
Propagation Delay vs Source Resistance
V
IN
=1V
STEP
0
1.6
2
15
5
Source Resistance (k
)
D
e
l
a
y
T
i
m
e
(
n
s
)
13
7.6
7.2
T
PD
-
T
PD
+
V
S
=5V
V
SD
=5V
R
L
=2.2k
0.4
1.2
0.8
11
7
9
V
S
=5V
V
SD
=5V
V
OD
=50mV
R
L
=2.2k
T
PD
-
T
PD
+
4
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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Typical Performance Curves
Propagation Delay vs Supply Voltage
4
4.2
4.8
5.2
5.4
5.6
6
6.8
6.6
6.2
6
5.8
5.6
V
S
(V)
D
e
l
a
y
T
i
m
e
(
n
s
)
6.4
4.4
Digital Supply Current vs Switching Frequency
(per comparator)
0
20
40
50
25
20
10
0
Frequency (MHz)
I
S
D
(
m
A
)
15
10
5
30
T
PD
-
T
PD
+
V
SD
=V
S
+
V
OD
=50mV
R
L
=2.2k
5
4.6
5.8
V
S
=5V
T
A
=25C
V
SD
=5V
V
SD
=3V
Output Low Voltage vs Temperature
-50
-30
10
30
50
70
90
0.285
0.235
Temperature (C)
V
O
L
(
V
)
-10
0.275
0.255
0.245
0.265
Supply Current vs Temperature
(per comparator)
-50
10
70
90
12
11
8
6
Temperature (C)
S
u
p
p
l
y
C
u
r
r
e
n
t
(
m
A
)
-30
7
50
10
9
30
-10
I
S
+
I
S
-
Propagation Delay vs Overdrive
V
IN
=1V
STEP
50 100
250 300
400
500
600
6.1
6
5.8
5.5
5.2
V
OD
(mV)
D
e
l
a
y
T
i
m
e
(
n
s
)
5.9
5.7
150
5.6
5.4
5.3
350
450
550
200
T
PD
-
T
PD
+
V
S
=5V
V
SD
=5V
R
L
=2.2k
Propagation Delay vs Overdrive
V
IN
=3V
STEP
0.2
0.6
0.8
1.2
1.6
2
8
6.5
5
V
OD
(mV)
D
e
l
a
y
T
i
m
e
(
n
s
)
7.5
7
6
5.5
1
1.4
1.8
0.4
T
PD
-
T
PD
+
V
S
=5V
V
SD
=5V
R
L
=2.2k
5
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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Typical Performance Curves
Output with 50MHz Input
V
IN
=1V
P-P
Output with 50MHz Input
V
IN
=3V
P-P
Output
(5ns/div,
2V/div)
Input
(5ns/div,
0.5nV/div)
Output
(5ns/div,
2V/div)
Input
(5ns/div,
2V/div)
Propagation Delay vs Load Capacitance
V
IN
=1V
STEP
0
10
30
40
50
80
100
9
5
C
LOAD
(pF)
D
e
l
a
y
T
i
m
e
(
n
s
)
20
8.5
6.5
5.5
7.5
8
6
7
60
90
70
V
S
=5V
V
SD
=5V
V
OD
=50mV
R
L
=2.2k
T
PD
-
T
PD
+
1087mW
QSO
P24 1
15C
/W
Power Dissipation vs Ambient Temperature
1.4
0
1
0.6
0.4
0.2
P
o
w
e
r
D
i
s
s
i
p
a
t
i
o
n
(
W
)
1.2
0.8
0
125
100
75
50
25
Ambient Temperature (C)
150
85
909mW
SO1
6
JA
=110
C/W
6
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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8
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Timing Diagram
V
IN
V
OD
t
h
t
s
t
pd
-
t
pw
(D)
t
d
+
Latch
Enable
Input
Latch
Compare
Latch
Latch
Compare
Differential
Input
Voltage
Comparator
Output
1.4V
V
OS
2.4V
Definition of Terms
Term
Definition
V
OS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
V
IN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
V
OD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
t
pd
+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
t
pd
-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
t
d
+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
t
d
-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
t
s
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
t
h
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
t
pw
(D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
7
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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Pin Descriptions
EL5485C
16-Pin SO
(0.150")
EL5486C
24-Pin
QSOP
Pin Name
Function
Equivalent Circuit
1
1
INA-
Negative input, channel A
Circuit 1
2
2
INA+
Positive input, channel A
(Reference circuit 1)
3,10,15,22
NC
Not Connected
3
4
GND
Digital ground
5
LATCHA
Latch input, channel A
Circuit 2
4
6
OUTA
Output, channel A
Circuit 3
5
7
OUTB
Output, channel B
(Reference circuit 3)
8
LATCHB
Latch input, channel B
(Reference circuit 2)
6
9
VS-
Negative supply voltage
7
11
INB+
Positive input, channel B
(Reference circuit 1)
8
12
INB-
Negative input, channel B
(Reference circuit 1)
9
13
INC-
Negative input, channel C
(Reference circuit 1)
10
14
INC+
Positive input, channel C
(Reference circuit 1)
11
16
VSD
Digital supply voltage
17
LATCHC
Latch input, channel C
(Reference circuit 2)
12
18
OUTC
Output, channel C
(Reference circuit 3)
13
19
OUTD
Output, channel D
(Reference circuit 3)
20
LATCHD
Latch input, channel D
(Reference circuit 2)
IN+
IN-
V
S
+
V
S
-
V
SD
V
S
+
V
S
-
LATCH
V
SD
V
S
+
V
S
-
OUT
8
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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5
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14
21
VS+
Positive supply voltage
15
23
IND+
Positive input, channel D
(Reference circuit 1)
16
24
IND-
Negative input, channel D
(Reference circuit 1)
Pin Descriptions
EL5485C
16-Pin SO
(0.150")
EL5486C
24-Pin
QSOP
Pin Name
Function
Equivalent Circuit
9
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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Applications Information
Power Supplies and Circuit Layout
The EL5485C and EL5486C comparators operate with
single and dual supply with 5V to 12V between V
S
+ and
V
S
-. The output side of the comparator is supplied by a
single supply from 2.7V to 5V. The rail to rail output
swing enables direct connection of the comparator to
both CMOS and TTL logic circuits. As with many high
speed devices, the supplies must be well bypassed. Elan-
tec recommends a 4.7F tantalum in parallel with a
0.1F ceramic. These should be placed as close as possi-
ble to the supply pins. Keep all leads short to reduce
stray capacitance and lead inductance. This will also
minimize unwanted parasitic feedback around the com-
parator. The device should be soldered directly to the PC
board instead of using a socket. Use a PC board with a
good, unbroken low inductance ground plane. Good
ground plane construction techniques enhance stability
of the comparators.
Input Voltage Considerations
The EL5485C and EL5486C's input range is specified
from 0.1V below V
S
- to 2.25V below V
S
+. The criterion
for the input limit is that the output still responds cor-
rectly to a small differential input signal. The differential
input stage is a pair of PNP transistors, therefore, the
input bias current flows out of the device. When either
input signal falls below the negative input voltage limit,
the parasitic PN junction formed by the substrate and the
base of the PNP will turn on, resulting in a significant
increase of input bias current. If one of the inputs goes
above the positive input voltage limit, the output will
still maintain the correct logic level as long as the other
input stays within the input range. However, the propa-
gation delay will increase. When both inputs are outside
the input voltage range, the output becomes unpredict-
able. Large differential voltages greater than the supply
voltage should be avoided to prevent damages to the
input stage.
Input Slew Rate
Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain min-
imum slew rate requirements. In some applications, it
may be helpful to apply some positive feedback (hyster-
esis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5485C and EL5486C, the propagation delay
increases when the input slew rate increases for low
overdrive voltages. With high overdrive voltages, the
propagation delay does not change much with the input
slew rate.
Latch Pin Dynamics
The EL5486C contains a "transparent" latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is con-
nected to a logic high level or left floating, the
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
remains latched to its value just before the latch's high-
to-low transition. To guarantee data retention, the input
signal must remain the same state at least 1ns (hold time)
after the latch goes low and at least 2ns (setup time)
before the latch goes low. When the latch goes high, the
new data will appear at the output in approximately 6ns
(latch propagation delay). The EL5485C does not have
latch inputs.
Hysteresis
Hysteresis can be added externally. The following two
methods can be used to add hysteresis.
Inverting comparator with hysteresis:
R
3
adds a portion of the output to the threshold set by R
1
and R
2
. The calculation of the resistor values are as
follows:
+
-
R
3
V
IN
V
REF
R
2
R
1
10
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
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Select the threshold voltage V
TH
and calculate R
1
and
R
2
. The current through R
1
/R
2
bias string must be many
times greater than the input bias current of the
comparator:
Let the hysteresis be V
H
, and calculate R
3
:
where:
V
O
=V
SD
-0.8V (swing of the output)
Recalculate R
2
to maintain the same value of V
TH
:
Non inverting comparator with hysteresis:
R
3
adds a portion of the output to the positive input.
Note that the current through R
3
should be much greater
than the input bias current in order to minimize errors.
The calculation of the resistor values as follows:
Pick the value of R
1
. R
1
should be small (less than 1k
)
in order to minimize the propagation delay time.
Choose the hysteresis V
H
and calculate R
3
:
Check the current through R
3
and make sure that it is
much greater than the input bias current as follows:
The above two methods will generate hysteresis of up to
a few hundred millivolts. Beyond that, the impedance of
R
3
is low enough to affect the bias string and adjustment
of R
1
may be required.
Power Dissipation
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
T
JMAX
(125C).
An approximate equation for the device power dissipa-
tion is as follows. Assume the power dissipation in the
load is very small:
where:
V
S
is the analog supply voltage from V
S
+ to V
S
-
I
S
is the analog quiescent supply current per comparator
V
SD
is the digital supply voltage from V
SD
to ground
I
SD
is the digital supply current per comparator
I
SD
strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipa-
tion, the maximum junction temperature can be
determined as follows:
where:
T
MAX
is the maximum ambient temperature
JA
is the thermal resistance of the package
Threshold Detector
The inverting input is connected to a reference voltage
and the non-inverting input is connected to the input. As
the input passes the V
REF
threshold, the comparator's
V
TH
V
REF
R
1
R
1
R
2
+
-------------------
=
R
3
V
O
V
H
--------
R
1
(
R
2
)
||
=
R
2
1
V
REF
(
V
TH
)
V
TH
R
1
-----------
V
TH
0.5V
SD
R
3
-------------------------------------
+
=
+
-
R
3
V
IN
V
REF
R
1
R
3
V
(
SD
0.8
)
R
1
V
H
--------
=
I
0.5V
SD
V
REF
R
3
----------------------------------------
=
P
DISS
V
S
I
S
V
SD
I
SD
)
+
(
=
T
JMAX
T
MAX
JA
P
DISS
+
=
11
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
E
L
5
4
8
5
C
,
E
L
5
4
8
6
C
-
P
r
e
l
i
m
i
n
a
r
y
output changes state. The non-inverting and inverting
inputs may be reversed.
Crystal Oscillator
A simple crystal oscillator using one comparator of an
EL5485C and EL5486C is shown below. The resistors
R
1
and R
2
set the bias point at the comparator's non-
inverting input. Resistors R
3
, R
4
, and C
1
set the invert-
ing input node at an appropriate DC average voltage
based on the output. The crystal's path provides resonant
positive feedback and stable oscillation occurs.
Although the EL5485C and EL5486C will give the cor-
rect logic output when an input is outside the common
mode range, additional delays may occur when it is so
operated. Therefore, the DC bias voltages at the inputs
are set about 500mV below the center of the common
mode range and the 200
resistor attenuates the feed-
back to the non-inverting input. The circuit will operate
with most AT-cut crystal from 1MHz to 8MHz over a
2V to 7V supply range. The output duty cycle for this
circuit is roughly 50% at 5V V
CC
, but it is affected by
the tolerances of the resistors. The duty cycle can be
adjusted by changing V
CC
value.
+
-
V
IN
V
REF
V
OUT
+
-
200
V
OUT
R
4
R
3
5V
1MHz to
8MHz
2k
C
1
0.01F
5k
1.5k
2k
R
1
R
2
12
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
E
L
5
4
8
5
C
,
E
L
5
4
8
6
C
-
P
r
e
l
i
m
i
n
a
r
y
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir-
cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con-
templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan-
tec, Inc.'s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
S
e
p
t
e
m
b
e
r
7
,
2
0
0
1
Printed in U.S.A.
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
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