Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a "controlled document". Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
2002 Elantec Semiconductor, Inc.
E
L
5185C
General Description
The EL5185C comparator is designed for operation in single supply
and dual supply applications with 5V to 12V between V
S
+ and V
S
-.
For single supplies, the inputs can operate from 0.1V below ground for
use in ground-sensing applications.
The output side of the comparator can be supplied from a single sup-
ply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5185C can be used to hold the comparator
output value by applying a low logic level to the pin.
The EL5185C is available in the 8-pin SO package and is specified for
operation over the -40C to +85C temperature range. Also available
are dual (EL5285C), window comparator (EL5287C), and quad
(EL5485C and EL5486C) versions.
Pin Configuration
1
2
3
4
8
7
6
5
VS+
L
A
T
C
H
VSD
OUT
GND
LATCH
IN+
IN-
VS-
EL5185CS
(8-Pin SO)
-
+
Features
4ns typ. propagation delay
5V to 12V input supply
+2.7V to +5V output supply
True-to-ground input
Rail-to-rail outputs
Active low latch
Dual available (EL5285C)
Window comparator (EL5287C)
Quad available (EL5485C &
EL5486C)
Pin-compatible 8ns family
available (EL5x81C, EL5283C &
EL5482C)
Applications
Threshold detection
High speed sampling circuits
High speed triggers
Line receivers
PWM circuits
High speed V/F converters
Ordering Information
Part No.
Package
Tape & Reel
Outline #
EL5185CS
8-Pin SO
-
MDP0027
EL5185CS-T7
8-Pin SO
7"
MDP0027
EL5185CS-T13
8-Pin SO
13"
MDP0027
EL5185C
4ns High-Speed Comparator
Janu
a
r
y
18,
2002
2
EL5185C
4ns High-Speed Comparator
E
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51
85C
Absolute Maximum Ratings
(T
A
= 25C)
Absolute maximum ratings are those values beyond which the device
could be permanently damaged. Absolute maximum ratings are stress
ratings only and functional device operation is not implied.
Analog Supply Voltage (V
S
+ to V
S
-)
+12.6V
Digital Supply Voltage (V
SD
to GND)
+7V
Differential Input Voltage
[(V
S
-) -0.2V] to [(V
S
+) +0.2V]
Common-mode Input Voltage
[(V
S
-) -0.2V] to [(V
S
+) +0.2V]
Latch Input Voltage
-0.2V to [(V
SD
)
+0.2V]
Storage Temperature Range
-65C to +150C
Ambient Operating Temperature
-40C to +85C
Operating Junction Temperature
125C
Power Dissipation
See Curves
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
.
Electrical Characteristics
V
S
= 5V, V
SD
= 5V, R
L
= 2.3k
, T
A
= 25C, unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
Unit
Input
V
OS
Input Offset Voltage
V
CM
= 0V, V
O
= 2.5V
1
4
mV
I
B
Input Bias Current
-10
-5
A
C
IN
Input Capacitance
5
pF
I
OS
Input Offset Current
V
CM
= 0V, V
O
= 2.5V
-2.5
0.5
2.5
A
V
CM
Input Voltage Range
(V
S
-) - 0.1
(V
S
+) - 2.25
V
CMRR
Common-mode Rejection Ratio
-5.1V < V
CM
< +2.75V
65
90
dB
Output
V
OH
Output High Voltage
V
IN
> 250mV
V
SD
- 0.6
V
SD
- 0.4
V
V
OL
Output Low Voltage
V
IN
> 250mV
GND + 0.25
GND + 0.5
V
Dynamic Performance
t
pd
+
Positive Going Delay Time
V
IN
= 1V
P-P
, V
OD
= 50mV
4
6
ns
t
pd
-
Negative Going Delay Time
V
IN
= 1V
P-P
, V
OD
= 50mV
4
6
ns
Supply
I
S
+
Positive Analog Supply Current
Per comparator
12
13.5
mA
I
S
-
Negative Analog Supply Current
Per comparator
7.5
8.5
mA
I
SD
Digital Supply Current at No Load
Per comparator, output high
5.5
6.5
mA
Per comparator, output low
0.9
1.2
mA
PSRR
Power Supply Rejection Ratio
55
80
dB
Latch
V
LH
Latch Input Voltage High
2.0
V
V
LL
Latch Input Voltage Low
0.8
V
I
LH
Latch Input Current High
V
LH
= 3.0V
-30
-18
A
I
LL
Latch Input Current Low
V
LL
= 0.3V
-30
-24
A
t
d
+
Latch Disable to High Delay
4
ns
t
d
-
Latch Disable to Low Delay
4
ns
t
s
Minimum Setup Time
2
ns
t
h
Minimum Hold Time
1
ns
t
pw
(D)
Minimum Latch Disable Pulse Width
5
ns
3
EL5185C
4ns High-Speed Comparator
E
L
5185C
Typical Performance Curves
Offset Voltage vs Temperature
-50
-30
10
30
50
70
90
2.5
2
1
0.5
0
-0.5
Temperature (C)
V
OS
(m
V
)
1.5
-10
Output Low Voltage vs Temperature
-50
-30
10
30
50
70
90
Temperature (C)
V
OL
(V
)
-10
Output High Voltage vs Temperature
-50
-30
10
30
50
70
90
Temperature (C)
V
OH
(V
)
-10
Input Bias Current vs Temperature
-50
-30
30
50
90
9
8
4
3
2
1
Temperature (C)
IB (
A
)
6
-10
10
70
7
5
Supply Current vs Supply Voltage
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
V
S
(V)
I
S
(m
A
)
I
S
+
I
S
-
V
IN
=-50mV
R
L
=2.3k
Supply Current vs Temperature (per comparator)
14
12
10
8
6
4
2
0
-50
-30
10
30
50
70
90
Temperature (C)
Su
p
p
l
y
Cu
r
r
e
n
t (
m
A)
I
S
+
I
S
-
-10
0.4
0.1
0.2
0.3
4.8
4.4
4.2
4
5
4.6
4
EL5185C
4ns High-Speed Comparator
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51
85C
Typical Performance Curves
Digital Supply Current vs Switching Frequency
(per comparator)
0
20
40
50
25
20
10
0
Frequency (MHz)
I
SD
(m
A
)
15
10
5
30
V
S
=5V
T
A
=25C
R
L
=2.3k
V
SD
=5V
V
SD
=3V
Propagation Delay vs Overdrive
V
IN
=1V
STEP
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
50 100
200
300
400
500
600
V
OD
(mV)
D
e
l
a
y T
i
m
e
(
n
s)
T
PD
+
T
PD
-
150
250
350
450
550
V
S
=5V
V
SD
=5V
R
L
=2.3k
Propagation Delay vs Overdrive
V
IN
=3V
STEP
6.8
6.6
6.4
6.2
6
5.8
5.4
5
0.2
0.4
0.8
1
1.2
1.6
2
V
OD
(V)
D
e
l
ay T
i
m
e
(
n
s)
T
PD
+
T
PD
-
0.6
1.4
1.8
V
S
=5V
V
SD
=5V
R
L
=2.3k
5.6
5.2
Propagation Delay vs Overdrive
V
IN
=5V
STEP
7.2
7
6.8
6.6
6.4
6.2
6
5.8
0.2 0.4
1
1.4
1.8
2.2
2.6
V
OD
(V)
D
e
l
ay T
i
m
e
(
n
s)
T
PD
+
T
PD
-
0.6
1.2
1.6
2
2.4
V
S
=5V
V
SD
=5V
R
L
=2.3k
0.8
Propagation Delay vs Source Resistance
V
IN
=1V
STEP
16
14
10
6
4
0
0.2
0.8
1.2
1.6
1.8
2
Source Resistance (k
)
D
e
l
ay T
i
m
e
(
n
s)
T
PD
+
T
PD
-
0.4
1
1.4
0.6
12
8
V
S
=5V
V
SD
=5mV
V
OD
=50mV
R
L
=2.3k
Propagation Delay vs Supply Voltage
4.5
4.4
4.2
4
3.8
3.7
3.6
3.5
4
4.2
4.8
5.2
5.6
5.8
6
V
S
(V)
D
e
l
a
y T
i
m
e
(
n
s)
T
PD
+
T
PD
-
4.4
5
5.4
V
SD
=V
S
+
V
OD
=50mV
R
L
=2.2k
4.6
4.3
4.1
3.9
5
EL5185C
4ns High-Speed Comparator
E
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5185C
Typical Performance Curves
Output with 50MHz Input
V
IN
=1V
P-P
Output with 50MHz Input
V
IN
=3V
P-P
Output
(5ns/div,
2V/div)
Input
(5ns/div,
0.5V/div)
Output
(5ns/div,
2V/div)
Input
(5ns/div,
2V/div)
Package Power Dissipation vs Ambient Temp.
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
0.7
0
0.5
0.3
0.2
0.1
P
o
w
e
r
D
i
ssi
p
a
t
i
o
n
(
W
)
0.6
0.4
0
125
100
75
50
25
Ambient Temperature (C)
150
85
625mW
16
0C
/W
SO
8
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity Test Board
1.4
1.2
1
0.8
0.6
0.4
0.2
0
150
125
100
75
50
25
0
85
Ambient Temperature (C)
P
o
w
e
r
D
i
s
s
i
pa
t
i
on
(
W
)
909mW
110
C/W
SO
8
Propagation Delay vs Load Capacitance
V
IN
=1V
STEP
7.5
7
6
5
4
0
10
40
60
80
90
100
C
LOAD
(pF)
D
e
l
a
y T
i
m
e
(
n
s)
T
PD
+
T
PD
-
20
50
70
30
6.5
5.5
V
S
=5V
V
SD
=5V
V
OD
=50mV
R
L
=2.3k
4.5
6
EL5185C
4ns High-Speed Comparator
E
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51
85C
Timing Diagram
V
IN
V
OD
t
h
t
s
t
pd
-
t
pw
(D)
t
d
+
Latch
Enable
Input
Latch
Compare
Latch
Latch
Compare
Differential
Input
Voltage
Comparator
Output
1.4V
V
OS
2.4V
Definition of Terms
Term
Definition
V
OS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
V
IN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
V
OD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
t
pd
+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
t
pd
-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
t
d
+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
t
d
-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
t
s
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
t
h
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
t
pw
(D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
7
EL5185C
4ns High-Speed Comparator
E
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5185C
Pin Descriptions
Pin Number
Pin Name
Function
Equivalent Circuit
1
VS+
Positive supply voltage
2
IN+
Positive input
Circuit 1
3
IN-
Negative input
(Reference Circuit 1)
4
VS-
Negative supply voltage
5
LATCH
Latch input
Circuit 2
6
GND
Digital ground
7
OUT
Output
Circuit 3
8
VSD
Digital Supply
IN+
IN-
V
S
+
V
S
-
V
SD
V
S
+
V
S
-
LATCH
V
SD
V
SD
V
S
+
V
S
-
OUT
8
EL5185C
4ns High-Speed Comparator
E
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51
85C
Applications Information
Power Supplies and Circuit Layout
The EL5185C comparator operates with single and dual
supply with 5V to 12V between V
S
+ and V
S
-. The out-
put side of the comparator is supplied by a single supply
from 2.7V to 5V. The rail to rail output swing enables
direct connection of the comparator to both CMOS and
TTL logic circuits. As with many high speed devices,
the supplies must be well bypassed. Elantec recom-
mends a 4.7 F tantalum in parallel with a 0.1 F
ceramic. These should be placed as close as possible to
the supply pins. Keep all leads short to reduce stray
capacitance and lead inductance. This will also mini-
m i z e u n wa n t e d p a r a s i t i c f e e d b a c k a r o u n d t h e
comparator. The device should be soldered directly to
the PC board instead of using a socket. Use a PC board
with a good, unbroken low inductance ground plane.
Good ground plane construction techniques enhance sta-
bility of the comparators.
Input Voltage Considerations
The EL5185C input range is specified from 0.1V below
V
S
- to 2.25V below V
S
+. The criterion for the input
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a
pair of PNP transistors, therefore, the input bias current
flows out of the device. When either input signal falls
below the negative input voltage limit, the parasitic PN
junction formed by the substrate and the base of the PNP
will turn on, resulting in a significant increase of input
bias current. If one of the inputs goes above the positive
input voltage limit, the output will still maintain the cor-
rect logic level as long as the other input stays within the
input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differ-
ential voltages greater than the supply voltage should be
avoided to prevent damages to the input stage.
Input Slew Rate
Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain min-
imum slew rate requirements. In some applications, it
may be helpful to apply some positive feedback (hyster-
esis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5185C, the propagation delay increases when the
input slew rate increases for low overdrive voltages.
With high overdrive voltages, the propagation delay
does not change much with the input slew rate.
Latch Pin Dynamics
The EL5185C contains a "transparent" latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is con-
ne cte d to a lo gic h ig h lev el or le ft flo ati ng , th e
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
remains latched to its value just before the latch's high-
to-low transition. To guarantee data retention, the input
signal must remain the same state at least 1ns (hold time)
after the latch goes low and at least 2ns (setup time)
before the latch goes low. When the latch goes high, the
new data will appear at the output in approximately 4ns
(latch propagation delay).
Hysteresis
Hysteresis can be added externally. The following two
methods can be used to add hysteresis.
Inverting comparator with hysteresis:
R
3
adds a portion of the output to the threshold set by R
1
and R
2
. The calculation of the resistor values are as
follows:
Select the threshold voltage V
TH
and calculate R
1
and
R
2
. The current through R
1
/R
2
bias string must be many
+
-
R
3
V
IN
V
REF
R
2
R
1
9
EL5185C
4ns High-Speed Comparator
E
L
5185C
ti me s g re a te r th a n t he in p u t b ia s c ur re n t o f th e
comparator:
Let the hysteresis be V
H
, and calculate R
3
:
where:
V
O
=V
SD
-0.8V (swing of the output)
Recalculate R
2
to maintain the same value of V
TH
:
Non inverting comparator with hysteresis:
R
3
adds a portion of the output to the positive input.
Note that the current through R
3
should be much greater
than the input bias current in order to minimize errors.
The calculation of the resistor values as follows:
Pick the value of R
1
. R
1
should be small (less than 1k
)
in order to minimize the propagation delay time.
Choose the hysteresis V
H
and calculate R
3
:
Check the current through R
3
and make sure that it is
much greater than the input bias current as follows:
The above two methods will generate hysteresis of up to
a few hundred millivolts. Beyond that, the impedance of
R
3
is low enough to affect the bias string and adjustment
of R
1
may be required.
Power Dissipation
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
T
JMAX
(125C).
An approximate equation for the device power dissipa-
tion is as follows. Assume the power dissipation in the
load is very small:
where:
V
S
is the analog supply voltage from V
S
+ to V
S
-
I
S
is the analog quiescent supply current per comparator
V
SD
is the digital supply voltage from V
SD
to ground
I
SD
is the digital supply current per comparator
I
SD
strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipa-
tio n, th e ma ximu m j un ct ion temp er atu re c an b e
determined as follows:
where:
T
MAX
is the maximum ambient temperature
JA
is the thermal resistance of the package
Threshold Detector
The inverting input is connected to a reference voltage
and the non-inverting input is connected to the input. As
the input passes the V
REF
threshold, the comparator's
V
T H
V
R E F
R
1
R
1
R
2
+
-------------------
=
R
3
V
O
V
H
--------
R
1
(
R
2
)
||
=
R
2
1
V
R EF
(
V
TH
)
V
T H
R
1
-----------
V
T H
0.5 V
SD
R
3
-------------------------------------
+
=
+
-
R
3
V
IN
V
REF
R
1
R
3
V
(
S D
0.8
)
R
1
V
H
--------
=
I
0.5 V
S D
V
R E F
R
3
----------------------------------------
=
P
D I SS
V
S
I
S
V
SD
I
S D
)
+
(
=
T
J M A X
T
M A X
J A
P
D IS S
+
=
10
EL5185C
4ns High-Speed Comparator
E
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51
85C
output changes state. The non-inverting and inverting
inputs may be reversed.
Crystal Oscillator
A simple crystal oscillator using one comparator of an
EL5185C is shown below. The resistors R
1
and R
2
set
the bias point at the comparator's non-inverting input.
Resistors R
3
, R
4
, and C
1
set the inverting input node at
an appropriate DC average voltage based on the output.
The crystal's path provides resonant positive feedback
and stable oscillation occurs. Although the EL5185C
will give the correct logic output when an input is out-
side the common mode range, additional delays may
occur when it is so operated. Therefore, the DC bias
voltages at the inputs are set about 500mV below the
center of the common mode range and the 200
resistor
attenuates the feedback to the non-inverting input. The
circuit will operate with most AT-cut crystal from 1MHz
to 8MHz over a 2V to 7V supply range. The output duty
cycle for this circuit is roughly 50% at 5V V
CC
, but it is
affected by the tolerances of the resistors. The duty cycle
can be adjusted by changing V
CC
value.
+
-
V
IN
V
REF
V
OUT
+
-
200
V
OUT
R
4
R
3
5V
1MHz to
8MHz
2k
C
1
0.01F
5k
1.5k
2k
R
1
R
2
11
EL5185C
4ns High-Speed Comparator
E
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51
85C
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir-
cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con-
templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan-
tec, Inc.'s warrant y is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
Janua
r
y
18,
2002
Printed in U.S.A.
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
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