This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only

FEATURES

Single power supply operation

- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors.

Manufactured on 0.18 µm triple-metal double

poly triple-well CMOS Flash Technology

High performance

- Access times as fast as 55 ns

Low power consumption (typical values at 5

MHz)

- 7 mA typical active read current
- 15 mA typical program/erase current
- 1

A typical standby current (standard access

time to active mode)

Flexible Sector Architecture:

- One 16-Kbyte, two 8-Kbyte, one 32-Kbyte,

and fifteen 64-Kbyte sectors (byte mode)

- One 8-Kword, two 4-Kword, one 16-Kword
and fifteen 32-Kword sectors (word mode)

Sector protection:

- Hardware locking of sectors to prevent

program or erase operations within individual
sectors

Additionally, temporary Sector Unprotect

allows code changes in previously locked
sectors.

High performance program/erase speed

- Byte/Word program time: 8µs typical
- Sector erase time: 500ms typical

JEDEC Standard Embedded Erase and

Program Algorithms

JEDEC standard DATA# polling and toggle

bits feature

Single Sector and Chip Erase

Sector Unprotect Mode

Erase Suspend / Resume modes:

Read or program another Sector during
Erase Suspend Mode

Low Vcc write inhibit < 2.5V

Minimum 1,000K endurance cycle

Package Options

- 48-pin TSOP (Type 1)

- 48-ball 6mm x 8mm FBGA

Commercial and industrial temperature

Range

GENERAL DESCRIPTION

The EN29LV800A is an 8-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 1,048,576 bytes or 524,288 words. Any byte can be programmed typically in 8µs.
The EN29LV800A features 3.0V voltage read and write operation, with access time as fast as 55ns
to eliminate the need for WAIT statements in high-performance microprocessor systems.

The EN29LV800A has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)
controls, which eliminate bus contention issues. This device is designed to allow either single

Sector or full chip erase operation, where each sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain
a minimum of 1,000K program/erase cycles on each sector.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

CONNECTION DIAGRAMS

A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0

A15
A14
A13
A12
A11
A10

A9
A8

NC
NC

WE#

RESET#

NC
NC

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

Standard
TSOP

FBGA

Top View, Balls Facing Down

A13

RY/BY#

WE#

A12

RESET#

A17

A14

A10

A18

A15

A11

A16

DQ7

DQ2

DQ5

DQ0

BYTE#

DQ14

CE#

DQ10

DQ12

DQ8

DQ15/A-1

DQ13

OE#

DQ11

Vcc

DQ9

Vss

DQ6

Vss

DQ4

DQ1

DQ3

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE

ADDRESS RANGE

Sector

(X16) (X8)

SECTOR

SIZE

(Kbytes /

Kwords)

A18

A17

A16

A15 A14 A13 A12

18 7E000h-7FFFFh

FC000h-FFFFFh

16/8 1 1 1 1 1 1 X

17 7D000h-7DFFFh

FA000h-FBFFFh

8/4 1 1 1 1 1 0 1

16 7C000h-7CFFFh F8000h-F9FFFh 8/4 1 1 1 1 1 0 0

15 78000h-7BFFFh

F0000h

F7FFFh

32/16 1 1 1 1 0 X X

70000h-77FFFh

E0000h - EFFFFh

64/32

68000h-6FFFFh

D0000h - DFFFFh

64/32

60000h-6FFFFh

C0000h - CFFFFh

64/32

58000h-5FFFFh

B0000h - BFFFFh

64/32

50000h-57FFFh

A0000h - AFFFFh

64/32

48000h-4FFFFh

90000h - 9FFFFh

64/32

40000h-47FFFh

80000h - 8FFFFh

64/32

38000h-3FFFFh

70000h - 7FFFFh

64/32

30000h-37FFFh

60000h - 6FFFFh

64/32

28000h-2FFFFh

50000h 5FFFFh

64/32

20000h-27FFFh

40000h 4FFFFh

64/32 0 1 0 0 X X X

18000h-1FFFFh

30000h 3FFFFh

64/32

10000h-17FFFh

20000h - 2FFFFh

64/32

08000h-0FFFFh

10000h - 1FFFFh

64/32

00000h-07FFFh

00000h - 0FFFFh

64/32

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE

ADDRESS RANGE

Sector

(X16) (X8)

SECTOR

SIZE

(Kbytes/
Kwords)

A18

A17

A16

A15 A14 A13 A12

78000h-7FFFFh

F0000h FFFFFh

64/32 1 1 1 1 X X X

70000h-77FFFh

E0000h EFFFFh

64/32 1 1 1 0 X X X

68000h-6FFFFh

D0000h DFFFFh

64/32

60000h-67FFFh

C0000h CFFFFh

64/32 1 1 0 0 X X X

58000h-5FFFFh

B0000h - BFFFFh

64/32

50000h-57FFFh

A0000h - AFFFFh

64/32

48000h-4FFFFh

90000h 9FFFFh

64/32 1 0 0 1 X X X

40000h-47FFFh

80000h 8FFFFh

64/32 1 0 0 0 X X X

10 38000h-3FFFFh

70000h

7FFFFh 64/32 0 1 1 1 X X X

30000h-37FFFh

60000h 6FFFFh

64/32 0 1 1 0 X X X

28000h-2FFFFh

50000h 5FFFFh

64/32

20000h-27FFFh

40000h 4FFFFh

64/32 0 1 0 0 X X X

18000h-1FFFFh

30000h 3FFFFh

64/32

10000h-17FFFh

20000h 2FFFFh

64/32 0 0 1 0 X X X

08000h-0FFFFh

10000h 1FFFFh

64/32

04000h-07FFFh

08000h 0FFFFh

32/16 0 0 0 0 1 X X

2 03000h-03FFFh 06000h

07FFFh

8/4 0 0 0 0 0 1 1

1 02000h-02FFFh 04000h

05FFFh

8/4 0 0 0 0 0 1 0

0 00000h-01FFFh 00000h

03FFFh

16/8 0 0 0 0 0 0 X

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

PRODUCT SELECTOR GUIDE

Product Number

EN29LV800A

Regulated Voltage Range: Vcc=3.0 3.6 V

-55R

Speed Option

Full Voltage Range: Vcc=2.7 3.6 V

-70

-90

Max Access Time, ns (

acc

)

55 70 90

Max CE# Access, ns (

)

55 70 90

Max OE# Access, ns (

)

30 30 35

BLOCK DIAGRAM

WE#

CE#

OE#

State

Control

Command

Erase Voltage Generator

Input/Output Buffers

Program Voltage

Generator

Chip Enable

Output Enable

Logic

Data Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

Timer

Vcc Detector

A0-A18

Vcc

Vss

DQ0-DQ15 (A-1)

ddr
e
s
s
L

a
t
c
h

Block Protect Switches

STB

RY/BY#

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

TABLE 3. OPERATING MODES

8M FLASH USER MODE TABLE

DQ8-DQ15

Operation CE# OE#

WE#

Reset#

A0-
A18 DQ0-DQ7

Byte#
= V

Read L

OUT

High-Z

Write L

High-Z

CMOS Standby

0.3V

0.3V X

High-Z

High-Z High-Z

TTL Standby

High-Z

High-Z High-Z

Output Disable

High-Z

High-Z High-Z

Hardware Reset

High-Z

High-Z High-Z

Temporary Sector
Unprotect X X

Notes:
L=logic low= V

, H=Logic High= V

, V

=11

0.5V, X=Don't Care (either L or H, but not floating!),

=Data In, D

OUT

=Data Out, A

=Address In

TABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)

8M FLASH MANUFACTURER/DEVICE ID TABLE

Description

Mode

A18

A12

A11

A10

A1 A0 DQ8

DQ15

DQ7 to

DQ0

Manufacturer ID:
Eon

L L H X X V

L L X

1Ch

Word L L H

22h

DAh

Device ID

(top boot
block)

Byte L L H

X X

X DAh

Word L L H

22h

5Bh

Device ID

(bottom boot
block)

Byte L L H

X X

X 5Bh

01h

(Protected)

Sector Protection
Verification

L L H SA X V

00h

(Unprotected)

Note:
1. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be
read with A8=H.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be

Vcc (CMOS logic level) for Command Autoselect Mode.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

USER MODE DEFINITIONS

Word / Byte Configuration

The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in
the byte or word configuration. When the Byte# Pin is set at logic `1', then the device is in word
configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.

On the other hand, if the Byte# Pin is set at logic `0', then the device is in byte configuration, and
only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-
DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Standby Mode

The EN29LV800A has a CMOS-compatible standby mode, which reduces the

current to

1µA

(typical). It is placed in CMOS-compatible standby when the CE# pin is at V

0.5. RESET# and

BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode,
which reduces the maximum V

current to < 1mA. It is placed in TTL-compatible standby when the

CE# pin is at V

. When in standby modes, the outputs are in a high-impedance state independent of

the OE# input.

Read Mode

The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. The device is also ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands" for more additional information.

The system must issue the reset command to re-enable the device for reading array data if DQ5
goes high, or while in the autoselect mode. See the "Reset Command" additional details.

Output Disable Mode

When the OE# pin is at a logic high level (V

), the output from the EN29LV800A is disabled. The

output pins are placed in a high impedance state.

Auto Select Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output on DQ15DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through the
command register.

When using programming equipment, the autoselect mode requires V

(10.5 V to 11.5 V) on

address pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In
addition, when verifying sector protection, the sector address must appear on the appropriate
highest order address bits. Refer to the corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are don't-care. When all necessary bits have
been set as required, the programming equipment may then read the corresponding identifier code
on DQ15DQ0.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

To access the autoselect codes in-system; the host system can issue the autoselect command via
the command register, as shown in the Command Definitions table. This method does not require
V

. See "Command Definitions" for details on using the autoselect mode.

Write Mode

Write operations, including programming data and erasing sectors of memory, require the host
system to write a command or command sequence to the device. Write cycles are initiated by
placing the byte or word address on the device's address inputs while the data to be written is input
on DQ[7:0] in Byte Mode (BYTE# = L) or on DQ[15:0] in Word Mode (BYTE# = H). The host system
must drive the CE# and WE# pins Low and the OE# pin High for a valid write operation to take place.
All addresses are latched on the falling edge of WE# and CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever happens first. The system is not required to
provide further controls or timings. The device automatically provides internally generated program /
erase pulses and verifies the programmed /erased cells' margin. The host system can detect
completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (Toggle) status bits.

The `Command Definitions' section of this document provides details on the specific device
commands implemented in the EN29LV800A.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector.
The hardware sector unprotection feature re-enables both program and erase operations in
previously protected sectors.

There are two methods to enabling this hardware protection circuitry. The first one requires only
that the RESET# pin be at VID and then standard microprocessor timings can be used to enable or
disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.
When doing Sector Unprotect, all the other sectors should be protected first.

The second method is meant for programming equipment. This method requires VID be applied to
both OE# and A9 pin and non-standard microprocessor timings are used. This method is described
in a separate document called EN29LV800A Supplement, which can be obtained by contacting a
representative of Eon Silicon Solution, Inc.

Temporary Sector Unprotect

Start

Reset#=V

(note 1)

Perform Erase or Program

Operations

Reset#=V

Temporary Sector

Unprotect Completed

(note 2)

This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Sector
Unprotect mode is activated by setting the RESET# pin to V

During this mode, formerly protected sectors can be programmed
or erased by simply selecting the sector addresses. Once is
removed from the RESET# pin, all the previously protected sectors
are protected again. See accompanying figure and timing
diagrams for more details.

Notes:
1. All protected sectors unprotected.
2. Previously protected sectors protected
again.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for t

acc

+ 30ns. The automatic sleep mode is

independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output is latched and always
available to the system. ICC

in the DC Characteristics table represents the automatic sleep more

current specification.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.

Low V

Write Inhibit

When Vcc is less than V

LKO

, the device does not accept any write cycles. This protects data during

Vcc power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V

LKO

. The

system must provide the proper signals to the control pins to prevent unintentional writes when Vcc
is greater than V

LKO

Write Pulse "Glitch" protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

, CE# = V

, or WE# = V

. To initiate a

write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE#
are all logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE# = V

, WE# = V

and OE# = V

, the device will not accept commands on the rising edge of

WE#.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

COMMAND DEFINITIONS

The operations of EN29LV800A are selected by one or more commands written into the command
register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase,
Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences
written at specific addresses via the command register. The sequences for the specified operation
are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values
or improper sequences will reset the device to Read Mode.

Table 5. EN29LV800A Command Definitions

Bus Cycles

Cycle

Command

Sequence

Cycles

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset 1

xxx

Word 555 2AA

555

000/
100

7F/
1C

Manufacturer
ID

Byte

AAA

555

AAA

000/
200

7F/
1C

Word 555 2AA

555 X01

22DA

Device ID
Top Boot

Byte

AAA

555

AAA

X02

Word 555 2AA

555 X01

225B

Device ID
Bottom Boot

Byte

AAA

555

AAA

X02

XX00

Word 555

2AA

555

(SA)
X02

XX01

Autoselect

Sector Protect
Verify

Byte

AAA

555

AAA

(SA)
X04

Word 555 2AA

555

Program

Byte

AAA

555

AAA

A0 PA PD

Word 555 2AA

555

Unlock Bypass

Byte

AAA

555

AAA

Unlock Bypass Program

XXX A0

Unlock Bypass Reset

XXX 90

XXX

Word 555 2AA

555 555

2AA 555

Chip Erase

Byte

AAA

555

AAA

555

AAA

Word 555 2AA

555 555

2AA

Sector Erase

Byte

AAA

555

AAA

555

55 SA 30

Erase Suspend

xxx

Erase Resume

xxx

Address and Data values indicated in hex
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don't-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A18-A12 uniquely select any Sector.

Reading Array Data

The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program
or Embedded Erase algorithm.

Following an Erase Suspend command, Erase Suspend mode is entered. The system can read
array data using the standard read timings, with the only difference in that if it reads at an address
within erase suspended sectors, the device outputs status data. After completing a programming

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

operation in the Erase Suspend mode, the system may once again read array data with the same
exception.

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See next section for details on Reset.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are
don't-care for this command.

The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading array data. Once erasure begins, however,
the device ignores reset commands until the operation is complete. The reset command may be
written between the sequence cycles in a program command sequence before programming begins.
This resets the device to reading array data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores reset commands until the operation is
complete.

The reset command may be written between the sequence cycles in an autoselect command
sequence. Once in the autoselect mode, the reset command must be written to return to reading
array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device
to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. The Command Definitions table shows
the address and data requirements. This is an alternative to the method that requires V

address bit A9 and is intended for PROM programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 4 any
number of times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array
data.

Word / Byte Programming Command

The device may be programmed by byte or by word, depending on the state of the Byte# Pin.
Programming the EN29LV800A is performed by using a four bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of CE# or
WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.

Programming status may be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle
bit). When the program operation is successfully completed, the device returns to read mode and
the user can read the data programmed to the device at that address. Note that data can not be
programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When
programming time limit is exceeded, DQ5 will produce a logical "1" and a Reset command can
return the device to Read mode.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Unlock Bypass

To speed up programming operation, the Unlock Bypass Command may be used. Once this feature
is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the
normal four-cycle Program Command to program the device. This mode is exited after issuing the
Unlock Bypass Reset Command. The device powers up with this feature disabled.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations. The Command Definitions table shows the address and data requirements for the chip
erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write
Operation Status" for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations
tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for
timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by
writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are
then followed by the address of the sector to be erased, and the sector erase command. The
Command Definitions table shows the address and data requirements for the sector erase
command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by
using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits.
Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations
tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing
diagram for timing waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. This command is valid only
during the sector erase operation. The Erase Suspend command is ignored if written during the chip
erase operation or Embedded Program algorithm. Addresses are don't-cares when writing the
Erase Suspend command.

When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

After the erase operation has been suspended, the system can read array data from or program
data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for
erasure.) Normal read and write timings and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on DQ7DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See
"Write Operation Status" for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array
data within non-suspended sectors. The system can determine the status of the program operation
using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation
Status" for more information. The Autoselect command is not supported during Erase Suspend
Mode.

The system must write the Erase Resume command (address bits are don't-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.

WRITE OPERATION STATUS

DQ7: DATA# Polling

The EN29LV800A provides DATA# polling on DQ7 to indicate the status of the embedded
operations. The DATA# Polling feature is active during the embedded Programming, Sector Erase,
Chip Erase, and Erase Suspend. (See Table 6)

When the embedded Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the embedded Programming,
an attempt to read the device will produce the true data written to DQ7. For the embedded
Programming, DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the
four-cycle sequence.

When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7
output during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the
sixth WE# or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of
the WE# or CE# pulse for chip erase or sector erase.

DATA# Polling must be performed at any address within a sector that is being programmed or
erased and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the
address used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when
the output enable (OE#) is low. This means that the device is driving status information on DQ7 at
one instant of time and valid data at the next instant of time. Depending on when the system
samples the DQ7 output, it may read the status of valid data. Even if the device has completed the
embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.
The valid data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing
diagram is shown in Figure 8.

RY/BY#: Ready/Busy

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is
in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied
together in parallel with a pull-up resistor to Vcc.

In the output-low period, signifying Busy, the device is actively erasing or programming. This
includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the
device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.

DQ6: Toggle Bit I

The EN29LV800A provides a "Toggle Bit" on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by active OE# or CE#) will result in DQ6 toggling between "zero" and "one". Once
the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will
be read on the next successive attempts. During embedded Programming, the Toggle Bit is valid
after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the
Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector erase or chip erase.

In embedded Programming, if the sector being written to is protected, DQ6 will toggles for about 2

s, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase,

if all selected sectors are protected, DQ6 will toggle for about 100

s. The chip will then return to the

read mode without changing data in all protected sectors.

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the
program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a
1 when the device has successfully completed its operation and has returned to read mode, the user
must check again to see if the DQ6 is toggling after detecting a "1" on DQ5.

The DQ5 failure condition may appear if the system tries to program a "1" to a location that is
previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under
this condition, the device halts the operation, and when the operation has exceeded the timing limits,
DQ5 produces a "1." Under both these conditions, the system must issue the reset command to
return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the output on DQ3 can be used to determine
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip
erase command.) When sector erase starts, DQ3 switches from "0" to "1." This device does not
support multiple sector erase command sequences so it is not very meaningful since it immediately
shows as a "1" after the first 30h command. Future devices may support this feature.

DQ2: Erase Toggle Bit II

The "Toggle Bit" on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence. DQ2 toggles when the system reads at addresses within those sectors that have been

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2
cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by
comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to the following table to compare outputs for DQ2 and DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section "DQ2: Toggle Bit" explains the algorithm.
See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical
form.

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7DQ0 at least twice in a row to determine whether a toggle bit is
toggling. Typically, a system would note and store the value of the toggle bit after the first read. After
the second read, the system would compare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling,
the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the
system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive
read cycles, determining the status as described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Flowchart 6).

Write Operation Status

Operation

DQ7 DQ6 DQ5 DQ3 DQ2

RY/BY

Embedded Program

Algorithm

DQ7# Toggle

N/A

toggle

Standar

d Mode

Embedded Erase Algorithm

Toggle

Reading within Erase

Suspended Sector

Toggle

0 N/A

Toggle

Reading within Non-Erase

Suspended Sector

Data Data Data Data Data 1

Erase

Suspend

Mode

Erase-Suspend Program

DQ7#

Toggle

N/A

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Table 6. Status Register Bits

DQ Name

Logic

Level

Definition

`1'

Erase Complete or

erase Sector in Erase suspend

`0' Erase

On-Going

DQ7

Program Complete or

data of non-erase Sector

during Erase Suspend

DATA#

POLLING

DQ7#

Program On-Going

`-1-0-1-0-1-0-1-'

Erase or Program On-going

DQ6

Read during Erase Suspend

TOGGLE

BIT

`-1-1-1-1-1-1-1-`

Erase Complete

`1'

Program or Erase Error

5 ERROR

BIT

`0'

Program or Erase On-going

`1'

Erase operation start

ERASE

TIME BIT

`0'

Erase timeout period on-going

`-1-0-1-0-1-0-1-'

Chip Erase, Sector Erase or

Erase suspend on currently

addressed

Sector. (When DQ5=1, Erase

Error due to currently

addressed Sector. Program

during Erase Suspend on-

going at current address

TOGGLE

BIT

DQ2

Erase Suspend read on

non Erase Suspend Sector

Notes:

DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits DQ5
for Program or Erase Success.

DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5 Error Bit: set to "1" if failure in programming or erase

DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).

DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

DQ7 = Data?

DQ5 = 1?

DQ7 = Data?

Yes

Read Data

Start

Read Data (1)

Fail

Pass

Flowchart 5. DATA# Polling
Algorithm

Notes:
(1) This second read is necessary in case the
first read was done at the exact instant when
the status data was in transition.

Yes

DQ6 = Toggle?

DQ5 = 1?

DQ6 = Toggle?

Yes

Read Data twice

Start

Read Data twice (2)

Fail

Pass

Flowchart 6. Toggle Bit Algorithm

Notes:
(2) This second set of reads is necessary in case
the first set of reads was done at the exact
instant when the status data was in transition.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Flowchart 7a. In-System Sector Protect Flowchart

RESET# = V

Wait 1

First Write

Cycle =

60h?

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

Sector Protect: Write 60h
to sector addr with
A6 = 0, A1 = 1, A0 = 0

Wait 150

Verify Sector Protect:
Write 40h to sector
address with
A6 = 0, A1 = 1, A0 = 0

Wait 0.4

Read from sector

address with

A6 = 0, A1 = 1, A0

Data = 01h?

PLSCNT = 25?

Increment

PLSCNT

Device failed

Yes

Protect another

sector?

Yes

Sector Protect

complete

Write reset

command

Remove V

from RESET#

Yes

Reset

PLSCNT = 1

START

Sector Protect

Algorithm

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Flowchart 7b. In-System Sector Unprotect Flowchart

PLSCNT = 1

RESET# = V

Wait 1

First Write

Cycle = 60h?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector unprotect

address (see
Diagram 7a.)

Yes

Sector Unprotect: Write 60H to

sector address with A6 = 1,

A1 = 1, A0 = 0

Set up first sector

address

All sectors

protected?

Temporary Sector

Unprotect Mode

START

Wait 0.4

Verify Sector Unprotect:

Write 40h to sector address

with A6 = 1, A1 = 1, A0 =0

Read from sector address with

A6 = 1, A1 = 1, A0 = 0

Set up next sector

address

Yes

Sector Unprotect

complete

Write reset

command

Remove V

from

RESET#

Last sector

verified?

Data = 00h?

Wait 15 ms

Increment

PLSCNT

PLSCNT =

1000?

Sector
Unprotect
Algorithm

Yes

Device failed

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Table 7. DC Characteristics

= 0°C to 70°C or - 40°C to 85°C; V

= 2.7-3.6V)

Symbol Parameter

Test

Conditions

Min

Typ

Max Unit

Input Leakage Current

Vcc

±5

µA

Output Leakage Current

OUT

Vcc

±5

µA

Supply Current (read) TTL

(read) CMOS Byte

CC1

(read) CMOS Word

CE# = V

; OE# = V

;

f = 5MHz

7 20 mA

Supply Current (Standby - TTL)

CE# = V

BYTE# = RESET# =

Vcc ± 0.3V

(Note 1)

0.4

1.0

CC2

Supply Current (Standby - CMOS)

CE# = BYTE# =

RESET# = Vcc ± 0.3V

(Note 1)

5.0

µA

CC3

Supply Current (Program or Erase)

Byte program, Sector or

Chip Erase in progress

CC4

Automatic Sleep Mode

= Vcc ± 0.3 V

= Vss ± 0.3 V

5.0

µA

Input Low Voltage

-0.5

0.8

Input High Voltage

0.7 x

Vcc

Vcc ±

0.3

Output Low Voltage

= 4.0 mA

0.45

Output High Voltage TTL

= -2.0 mA

0.85 x

Vcc

Output High Voltage CMOS

= -100

Vcc -

0.4V

A9 Voltage (Electronic Signature)

10.5

11.5

A9 Current (Electronic Signature)

A9 = V

100

µA

LKO

Supply voltage (Erase and

Program lock-out)

2.3 2.5

Notes

1. BYTE# pin can also be GND

± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that

they draw power if not at full CMOS supply voltages.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

AC CHARACTERISTICS
Hardware Reset (Reset#)

Speed options

Unit

Parameter

Std

Description

Test

Setup

-55R -70 -90

READY

Reset# Pin Low to Read or Write

Embedded Algorithms

Max 20

READY

Reset# Pin Low to Read or Write

Non Embedded Algorithms

Max 500

Reset# Pulse Width

Min

500

Reset# High Time Before Read

Min

Reset# Timings

RY/BY#

0 V

RESET#

CE#
OE#

READY

Reset Timings NOT During Embbedded Algorithms

RESET#

CE#
OE#

RY/BY#

READY

Reset Timings During Embedded Algorithms

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Table 8. AC CHARACTERISTICS

Read-only Operations Characteristics

Parameter

Symbols

Speed Options

JEDEC Standard Description

Test

Setup

-55R -70 -90 Unit

AVAV

Read Cycle Time

Min 55 70 90 ns

AVQV

ACC

Address to Output Delay

CE# = V

OE#

Max

55 70 90 ns

ELQV

Chip Enable To Output Delay

OE# = V

Max

55 70 90 ns

GLQV

Output Enable to Output Delay

Max

30 30 35 ns

EHQZ

Chip Enable to Output High Z

Max

15 20 20 ns

GHQZ

Output Enable to Output High Z

Max

15 20 20 ns

AXQX

Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first

Min

0 0 0

Notes:
For 55R

Vcc = 3.0V ± 5%

Output Load : 1 TTL gate and 30pF

Input Rise and Fall Times: 5ns

Input Rise Levels: 0.0 V to Vcc

Timing

Measurement

Reference

Level, Input and Output: 1.5 V

For all others:

Vcc = 3.0V ± 5%
Output Load: 1 TTL gate and 100 pF

Input Rise and Fall Times: 5 ns

Input Pulse Levels: 0.0 V to Vcc

Timing

Measurement

Reference

Level, Input and Output: 1.5 V

Addresses

CE#

OE#

WE#

Outputs

Reset#

RY/BY#

HIGH Z

Output Valid

Addresses Stable

OEH

ACC

Figure 5. AC Waveforms for READ Operations

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Table 9. AC CHARACTERISTICS

Write (Erase/Program) Operations

Parameter

Symbols

Speed Options

JEDEC Standard Description

-55R -70 -90 Unit

AVAV

Write Cycle Time

Min 55 70 90 ns

AVWL

Address Setup Time

Min 0 0 0 ns

WLAX

Address Hold Time

Min 45 45 45 ns

DVWH

Data Setup Time

Min 25 30 45 ns

WHDX

Data Hold Time

Min 0 0 0 ns

OES

Output Enable Setup Time

Min 0 0 0 ns

Read

MIn 0

0 ns

OEH

Output Enable

Hold Time

Toggle and

DATA# polling

Min 10 10 10 ns

GHWL

Read Recovery Time before

Write (OE# High to WE# Low)

Min 0 0 0 ns

ELWL

CE# SetupTime

Min

WHEH

CE# Hold Time

Min

WLWH

Write Pulse Width

Min 30 35 45 ns

WHDL

WPH

Write Pulse Width High

Min 20 20 20 ns

Typ

8 8 8

µs

WHWH1

Programming Operation

(Word AND Byte Mode)

Max 200 200 200 µs

WHWH2

Sector Erase Operation

Typ 0.5 0.5 0.5 s

VCS

Vcc Setup Time

Min 50 50 50 µs

VIDR

Rise Time to V

Min

500 500 500 ns

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Table 10. AC CHARACTERISTICS
Write (Erase/Program) Operations

Alternate CE#

Controlled Writes

Parameter

Symbols

Speed Options

JEDEC Standard

Description

-55R -70 -90 Unit

AVAV

Write Cycle Time

Min 55 70 90 ns

AVEL

Address Setup Time

Min 0 0 0 ns

ELAX

Address Hold Time

Min 45 45 45 ns

DVEH

Data Setup Time

Min 25 30 45 ns

EHDX

Data Hold Time

Min 0 0 0 ns

OES

Output Enable Setup Time

Min 0 0 0 ns

Read

Min 0 0 0 ns

OEH

Output Enable
Hold Time

Toggle and
Data# Polling

Min 10 10 10 ns

GHEL

Read Recovery Time before
Write (OE# High to CE# Low)

Min 0 0 0 ns

WLEL

WE# SetupTime

Min 0 0 0 ns

EHWH

WE# Hold Time

Min 0 0 0 ns

ELEH

Write Pulse Width

Min 30 35 45 ns

EHEL

CPH

Write Pulse Width High

Min 20 20 20 ns

Typ 8 8 8 µs

WHWH

WHWH1

Programming Operation
(byte AND word mode)

Max 200 200 200 µs

WHWH

WHWH2

Sector Erase Operation

Typ 0.5 0.5 0.5 s

VCS

Vcc Setup Time

Min 50 50 50 µs

VIDR

Rise Time to V

Min

500 500 500 ns

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Table 11. ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Typ Max Unit

Comments

Sector Erase Time

0.5

sec

Chip Erase Time

sec

Excludes 00H programming prior

to erasure

Byte Programming Time

300

µs

Word Programming Time

300

µs

Byte 8.4

25.2

Chip Programming

Time

Word 4.2

12.6

sec

Excludes system level overhead

Erase/Program Endurance

100K

cycles

Minimum 100K cycles

Table 12. LATCH UP CHARACTERISTICS

Parameter Description

Min

Max

Input voltage with respect to V

on all pins except I/O pins

(including A9, Reset and OE#)

-1.0 V

12.0 V

Input voltage with respect to V

on all I/O Pins

-1.0 V

Vcc + 1.0 V

Vcc Current

-100 mA

100 mA

Note : These are latch up characteristics and the device should never be put under
these conditions. Refer to Absolute Maximum ratings for the actual operating limits.

Table 14. 48-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

= 0

6 7.5 pF

OUT

Output Capacitance

OUT

= 0

8.5 12 pF

IN2

Control Pin Capacitance

= 0

7.5 9 pF

Table 15. DATA RETENTION

Parameter Description

Test Conditions

Min

Unit

150°C 10

Years

Minimum Pattern Data Retention Time

125°C 20

Years

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

AC CHARACTERISTICS

Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings

Erase Command Sequence (last 2 cycles)

Read Status Data (last two cycles)

Addresses

Status

OUT

VCS

BUSY

WPH

GHWL

WHWH2

or t

WHWH3

0x2AA SA

0x55 0x30

0x555 for chip
erase

CE#

OE#

WE#

Data

RY/BY#

Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, D

out

=true data at read address.

2. V

shown only to illustrate t

vcs

measurement references. It cannot occur as shown during a valid command

sequence.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Figure 7. Program Operation Timings

Program Command Sequence (last 2 cycles)

Addresses

0x555 PA

CE#

GHWL

OE#

WE#

WPH

WHWH1

Data

PD Status

OUT

OxA0

BUSY

RY/BY#

VCS

Notes:
1. PA=Program Address, PD=Program Data, D

OUT

is the true data at the program address.

2. V

shown in order to illustrate t

VCS

measurement references. It cannot occur as shown during a valid

command sequence.

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm

Operations

Notes:

RY/BY#

DQ[6:0]

DQ[7]

WE#

OE#

CE#

Addresses

ACC

Valid Data

Status
Data

True

Comple-
ment

Status Data

Complement

BUSY

OEH

1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.

Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm

Operations

(stops toggling)

Valid Data

Valid Status

ACC

OEH

BUSY

VA VA

Valid Status

(first read)

(second

Addresses

CE#

OE#

WE#

DQ6, DQ2

RY/BY#

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Figure 10. Alternate CE#

Controlled Write Operation Timings

PA for Program
SA for Sector Erase
0x555 for Chip Erase

0x555 for Program
0x2AA for Erase

Notes:

PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
D

out

= array data read at VA

Shown above are the last two cycles of the program or erase command sequence and the last status read cycle
Reset# shown to illustrate t

measurement references. It cannot occur as shown during a valid command

sequence.

Figure 11. DQ2 vs. DQ6

DQ2

WE#

DQ6

Enter

Embedded

Erase

Suspend

Enter Erase

Suspend

Program

Erase

Resume

Erase Enter

Suspend

Read

Enter

Suspend

Program

Erase

Complete

Erase
Suspend
Read

OUT

Status

Reset#

RY/BY#

Data

CE#

OE#

WE#

Addresses

CPH

PD for Program
0x30 for Sector Erase
0x10 for Chip Erase

0xA0 for
Program

BUSY

CWHWH1

/ t

CWHWH2

/ t

CWHWH3

GHEL

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

Figure 12. Sector Protect/Unprotect Timing Diagram

SA,

A6,A1,A0

RESET#

VIDR

CE#

WE#

OE#

Vcc

60h 60h

Valid

Verify

Sector Protect/Unprotect

Sector Protect: 150 uS
Sector Unprotect: 15 mS

>0.4

40h Status

Valid

Data

Notes:
Use standard microprocessor timings for this device for read and write cycles.
For Sector Protect, use A6=0, A1=1, A0=0. For Sector Unprotect, use A6=1, A1=1, A0=0.

Temporary Sector Unprotect

Speed Option

Unit

Parameter

Std

Description

-55R -70 -90

VIDR

Rise and Fall Time

Min

500

RSP

RESET# Setup Time for Temporary

Sector Unprotect

Min

Figure 13. Temporary Sector Unprotect Timing Diagram

0 or 3 V

RESET#

RY/BY#

WE#

CE#

0 or 3 V

RSP

VIDR

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

ABSOLUTE MAXIMUM RATINGS

Parameter Value

Unit

Storage Temperature

-65 to +125

Plastic Packages

-65 to +125

Ambient Temperature

With Power Applied

-55 to +125

Output Short Circuit Current

200

A9, OE#, Reset#

-0.5 to +11.5

All other pins

-0.5 to Vcc+0.5

Voltage with

Respect to Ground

Vcc

-0.5 to +4.0

Notes:
1.

No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.

Minimum DC input voltage on A9, OE#, RESET# pins is 0.5V. During voltage transitions, A9, OE#, RESET# pins may
undershoot V

to 1.0V for periods of up to 50ns and to 2.0V for periods of up to 20ns. See figure below. Maximum DC

input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.

Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, inputs may undershoot V

to 1.0V for

periods of up to 50ns and to 2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O
pins is V

+ 0.5 V. During voltage transitions, outputs may overshoot to V

+ 1.5 V for periods up to 20ns. See figure

below.

Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.

RECOMMENDED OPERATING RANGES

Parameter Value

Unit

Ambient Operating Temperature

Commercial

Devices

Industrial

Devices

0 to 70

-40 to 85

Regulated: 3.0 to 3.6

Operating Supply Voltage

Vcc

Full: 2.7 to 3.6

Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc

+1.5V

Maximum Negative Overshoot Waveform

Maximum Positive Overshoot Waveform

Rev. C, Issue Date: 2005/01/10

This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.

EN29LV800A

ORDERING INFORMATION

EN29LV800A T - 70 T

C P

PACKAGING CONTENT

(Blank) = Conventional

P = Pb Free

TEMPERATURE RANGE

C = Commercial (0

C to +70

I = Industrial (-40

C to +85

PACKAGE
T = 48-pin TSOP

B = 48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80mm pitch, 6mm x 8mm package

SPEED

55R = 55ns (Regulated)
70 = 70ns

90 = 90ns

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

BASE PART NUMBER

EN = EON Silicon Solution Inc.

29LV = FLASH, 3V Read Program Erase

800 = 8 Megabit (1024K x 8 / 512K x 16)
A = version identifier

Rev. C, Issue Date: 2005/01/10

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EN29LV800A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EN29LV800A