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Электронный компонент: S1L9

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MF908-03
S1L9000F Series
DESIGN GUIDE
DESIGN GUIDE
GATE ARRAY
S1L9000F Series
st issue March, 1996 D
May, 2001 in Japan
C
A
NOTICE
No part of this material may be reproduced or duplicated in any from or by any means without the
written permission of EPSON. EPSON reserves the right to make changes to this material without
notice. EPSON does not assume any liability of any kind arising out of any inaccuracies contained
in this material or due to its application or use in any product or circuit and, further, there is no
representation that this material is applicable to products requiring high level reliability, such as,
medical products. Moreover, no license to any intellectual property rights is granted by implication
or otherwise, and there is no representation or warranty that anything made in accordance with
this marerial will be free from any patent or copyright infringement of a third party. This material or
portions there of may contain techology or the subject relating to strategic products under the
control of the Forign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of international Trade and Industry or other approval from another
government agency.
SEIKO EPSON CORPORATION 2001, All rights reserved.
The information of the product number change
Configuration of product number
Comparison table between new and previous number
Starting April 1, 2001 the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
DEVICES
S1
L
60843
F
00A0
Packing specification
Specifications
Shape (
2)
Model number
Model name (
1)
Product classification (S1:semiconductor)
00
Previous number
New Number
SLA9000F series
S1L9000F series
SLA902F S1L902F2
SLA904F S1L904F2
SLA907F S1L907F2
SLA909F S1L909F2
SLA913F S1L913F2
SLA919F S1L919F2
SLA927F S1L927F2
SLA944F S1L944F2
1: Model name
2: Shape
K Standard Cell
L
Gate Array
X Embedded Array
B Assembled on board, COB,
BGA
C Plastic DIP
D Bare Chip
F
Plastic QFP
H Ceramic DIP
L
Ceramic QFP
M Plastic SOP
R TABQFP
T
Tape Carrier (TAB)
2
TSOP (Standard Bent)
3
TSOP (Reverse Bent)
Contents
GATE ARRAY S1L9000F SERIES
EPSON
i
DESIGN GUIDE
S1L9000F Series Table of Contents
Chapter 1 Overview ....................................................................................... 1
1.1 Features of the S1L9000F Series................................................................... 1
1.2 Master Structure of the S1L9000F Series ...................................................... 2
1.3 Electrical Characteristics and Specifications of the S1L9000F Series ........... 3
1.4 Overview of Gate Array Development Flow ................................................... 5
Chapter 2 Estimating Gate Density and Selecting the Master....................... 7
2.1 Dividing Up Logic Between Chips .................................................................. 7
2.2 Estimating the number of gates used in S1L9000F Series ............................ 7
2.3 Estimating the Number of Input/Output Terminals ......................................... 7
2.4 Selecting the Master....................................................................................... 7
2.5 Estimating the BCs that can be Used in Circuits which Include RAM ............ 8
Chapter 3 Cautions and Notes Regarding Circuit Design.............................. 9
3.1 Inserting I/O Cells ........................................................................................... 9
3.2 The Use of Differentiating Circuits is Forbidden ............................................. 9
3.3 Wired Logic is Forbidden................................................................................ 9
3.4 Hazard Countermeasures ............................................................................ 10
3.5 Fan-out Constraints ...................................................................................... 10
3.6 Bus Circuits .................................................................................................. 10
3.7 Schematic Capture Guidelines ..................................................................... 11
3.8 Clock Tree Synthesis.................................................................................... 12
Chapter 4 Input/Output Cells and Their Use................................................ 15
4.1 Types of Input/Output Cells in the S1L9000F Series ................................... 15
4.1.1 Selecting I/O Cell ............................................................................................... 15
4.2 I/O Buffer Configurations .............................................................................. 16
4.2.1 I/O Buffer Configurations with a Single 5.0V Power Supply .............................. 16
4.2.1.1 Input Buffer Configurations with a Single 5.0V Power Supply.................................. 16
4.2.1.2 Output Buffer Configurations with a Single 5.0V Power Supply............................... 17
4.2.1.3 Bi-directional Buffer Configurations with a Single 5.0V Power Supply..................... 19
4.2.2 I/O Buffer Configurations with a Single 3.0 V/3.3 V Power Supply.................... 20
4.2.2.1 Input Buffer Configurations with a Single 3.0 V/3.3 V Power Supply ....................... 20
4.2.2.2 Output Buffer Configurations with a Single 3.0/3.3V Power Supply......................... 21
4.2.2.3 Bi-directional Buffer Configurations with a Single 3.0 V/3.3 V Power Supply .......... 23
4.3 Method of Structuring the Oscillator Circuit .................................................. 25
4.3.1 Oscillator Circuit Configurations ........................................................................ 25
4.3.2 Oscillator Circuit Considerations........................................................................ 25
Contents
ii
EPSON
GATE ARRAY S1L9000F SERIES
DESIGN GUIDE
Chapter 5 RAM ............................................................................................ 27
5.1 Features ....................................................................................................... 27
5.2 Word/Bit Structure and Simulation Model Selection .................................... 28
5.3 RAM Size ..................................................................................................... 29
5.4 Deciding RAM Placement on Master Slice .................................................. 30
5.5 Explanation of Functions.............................................................................. 31
5.6 Delay Parameters ........................................................................................ 33
5.7 Timing Charts............................................................................................... 41
5.8 RAM Test Method ........................................................................................ 44
5.9 RAM Current Consumption .......................................................................... 44
5.10 RAM Symbols and How They Are Used .................................................... 44
Chapter 6 Circuit Design Taking Testability Into Account ............................ 46
6.1 Considerations Regarding Circuit Initialization............................................. 46
6.2 Considerations Regarding Compressing the Test Patterns ......................... 46
6.3 RAM Test Circuit .......................................................................................... 46
6.3.1 RAM Test Pattterns............................................................................................47
6.4 Function Cell Test Circuits ........................................................................... 52
6.4.1 Test Circuit Structures .......................................................................................52
6.4.2 Test Patterns......................................................................................................52
6.4.3 Test Circuit Data ................................................................................................52
6.5 Test Circuit which Simplifies AC and DC Testing ........................................ 53
Chapter 7 Propagation Delay and Timing .................................................... 59
7.1 Simple Delay Models ................................................................................... 59
7.2 Load Due to Input Capacitance (Load A)..................................................... 60
7.3 Load Due to Interconnect Capacitance (Load B) ......................................... 61
7.4 Propagation Delay Calculations ................................................................... 61
7.5 Calculating Output Buffer Delay................................................................... 64
7.6 FF (flip-flop) Setup/Hold Times .................................................................... 64
7.7 Chip Internal Skew ....................................................................................... 67
Chapter 8 Test Pattern Generation .............................................................. 68
8.1 Testability Considerations ............................................................................ 68
8.2 Waveform Types .......................................................................................... 68
8.3 Constraints on the Types of Test Patterns................................................... 69
8.3.1 Test Rate and Number of Events.......................................................................69
8.3.2 Input Delay.........................................................................................................69
8.3.3 Pulse Width........................................................................................................69
8.3.4 Input Waveform Format .....................................................................................69
8.3.5 Strobe ................................................................................................................69