SRAM
AS5C4009LL
Austin Semiconductor, Inc.
AS5C4009LL
Rev. 4.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
AVAILABLE AS MILITARY
SPECIFICATION
SMD 5962-95613
1,2
MIL STD-883
1
FEATURES
Ultra Low Power with 2V Data Retention
(0.2mW MAX worst case Power-down standby)
Fully Static, No Clocks
Single +5V 10% power supply
Easy memory expansion with CE\ and OE\ options
All inputs and outputs are TTL-compatible
Three state outputs
Operating temperature range:
Ceramic -55
o
C to +125
o
C & -40
o
C to +85
o
C
Plastic -40
o
C to +85
o
C
3
1. Not applicable to plastic package
2. Applies to CW package only.
3. Contact factory for -55
o
C to +125
o
C
OPTIONS
MARKING
Timing
55ns access
-55
4
70ns access
-70
85ns access
-85
100ns access
-100
Packages
Ceramic Dip (600 mil)
CW
No. 112
Ceramic SOJ
5
ECJ
No. 502
Plastic TSOP
DG
No. 1002
PIN ASSIGNMENT
(Top View)
32-Pin DIP, 32-Pin SOJ
& 32-Pin TSOP
4. For DG package, contact factory
5. Contact Factory
NOTE: Not all combinations of operating temperature, speed, data retention and low power are
necessarily available. Please contact the factory for availability of specific part number
combinations.
512K x 8 SRAM
Ultra Low Power SRAM
For more products and information
please visit our web site at
www.austinsemiconductor.com
GENERAL DESCRIPTION
The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a
special ultra low power design process. ASI's pinout adheres to the
JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32
pin version allows for easy upgrades from the 1 meg SRAM design.
For flexibility in memory applications, ASI offers chip enable (CE\)
and output enable (OE\) capabilities. These features can place the
outputs in High-Z for additional flexibility in system design.
This devices operates from a single +5V power supply and all
inputs and outputs are fully TTL-compatible.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW. The device offers a re-
duced power standby mode when disabled, by lowering VCC to 2V and
maintaining
CE\ = 2V. This allows system designers to meet ultra low
standby power requirements.
Pin Name
Function
WE\
Write Enable Input
CE\
Chip Select Input
OE\
Output Enable Input
A0 - A18
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
Vcc
Power
Vss
Ground
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/01
I/02
I/03
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/08
I/07
I/06
I/05
I/04
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
AS5C4009LL
Rev. 4.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM
Clk. gen.
Precharge circuit
Memory Array
1024 rows
512 x 8 columns
Row
select
I/O Circuit
Control
logic
CE\
WE\
OE\
I/O
1
I/O
8
A18
A16
A14
A12
A7
A6
A4
A1
A0
A5
Column Select
Data
cont
Data
cont
A9
A8
A13
A17
A15
A10
A11
A3
A2
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
AS5C4009LL
Rev. 4.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss...................-.5V to +7.0V
Voltage on any pin Relative to Vss..........................-.5V to +7.0V
Storage Temperature ....................................-65
C to +150
C
Operating Temperature Range.............................-55
o
C to +125
o
C
Soldering Temperature Range...............................................260
o
C
Maximum Junction Temperature**....................................+150
C
Power Dissipation...................................................................1.0W
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
** Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
A
< 125
o
C; Vcc = 5V +10%)
PARAMETER/CONDITION
MIN
MAX
UNITS
NOTES
Input Leakage Current (V
IN
= V
SS
to V
CC
)
-5
5
Output Leakage Current
(CE\=V
IH
or OE\=V
IH
or WE\=V
IL
, V
IO
=V
SS
to V
CC
)
-5
5
Output Low Voltage (I
OL
= 2.1mA)
--
0.4
V
15
Output High Voltage (I
OH
= -1.0 mA)
2.4
--
V
15
Supply Voltage
4.5
5.5
V
15
Input High (Logic 1) Voltage
2.2
Vcc +0.5
V
1, 15
Input Low (Logic 0) Voltage
-0.5
0.8
V
2, 15
V
IL
SYMBOL
I
LI
I
LO
V
OL
V
OH
V
CC
V
IH
CONDITIONS
SYM
-55
-70
-85
-100
UNITS NOTES
Cycle Time = Min., 100%
Duty Cycle, I
IO
= 0mA,
CE\ = V
IL
, V
IN
= V
IH
or V
IL
I
cc1
100
90
80
70
mA
3
TTL
CE\ = V
IH
,
Other inputs = V
IL
or V
IH
I
SB
6
6
6
6
mA
CMOS
CE\ = Vcc -0.2V,
Other inputs = 0 ~ Vcc
I
SB1
0.75
0.75
0.75
0.75
mA
MAX
Power Supply Current:
Operating
PARAMETER
Power Supply Current:
Standby
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
AS5C4009LL
Rev. 4.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C < T
A
< 125
o
C; Vcc = 5V +10%)
CAPACITANCE
PARAMETER
SYMBOL
MAXIMUM
UNITS
NOTES
Input Capacitance
V
IN
=0V
C
IN
8
pF
4
Input/Output Capactiance
V
IO
=0V
C
IO
10
pF
4
T
A
= 25
o
C, f = 1MHz
V
CC
= 5V
CONDITIONS
SYM
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
READ Cycle
READ cycle Time
t
RC
55
70
85
100
ns
Address access time
t
AA
55
70
85
100
ns
Chip Enable access time
t
ACE
55
70
85
100
ns
Output hold from address change
t
OH
10
10
10
10
ns
Chip Enable to output in Low-Z
t
LZCE
10
10
10
10
ns
4,6
Chip disable to output in High-Z
t
HZCE
20
25
30
30
ns
4,6
Chip Enable to power-up time
t
PU
0
0
0
0
ns
4
Chip disable to power-down time
t
PD
55
70
85
100
ns
4
Output Enable access time
t
AOE
30
35
40
45
ns
Output Enable to output in Low-Z
t
LZOE
5
5
5
5
ns
4,6
Output disable to output in High-Z
t
HZOE
20
25
30
30
ns
4,6
WRITE Cycle
WRITE cycle time
t
WC
55
70
85
100
ns
Chip Enable to end of write
t
CW
50
60
70
80
ns
Address valid to end of write
t
AW
50
60
70
80
ns
Address setup time
t
AS
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
ns
WRITE pulse width
t
WP1
50
60
70
80
ns
Data setup time
t
DS
30
30
35
40
ns
Data hold time
t
DH
0
0
0
0
ns
Write disable to output in Low-Z
t
LZWE
5
5
5
5
ns
4,6
Write Enable to output in High-Z
t
HZWE
25
25
30
30
ns
4,6
-100
DESCRIPTION
-55
-70
-85
SRAM
AS5C4009LL
Austin Semiconductor, Inc.
AS5C4009LL
Rev. 4.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load ......................................... See Figures 1
NOTES
1.
Overshoot: Vcc +3.0V for pulse width < 20ms.
2.
Undershoot: -3V for pulse width < 20ms.
3.
I
CC
is dependent on output loading and cycle rates.
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE
, and
t
HZWE
is less than
t
LZWE
.
7.
WE\ is HIGH for READ cycle.
8.
Device is continuously selected. Chip enables and
output enables are held in their active state.
9.
Address valid prior to, or coincident with, latest
occurring chip enable.
10.
t
RC = Read Cycle Time.
11. Chip enable and write enable can initiate and
terminate a WRITE cycle.
12. Output enable (OE\) is inactive (HIGH).
13. Output enable (OE\) is active (LOW).
14. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150C. Care should be taken to limit power to
acceptable levels.
15. All voltage referenced to Vss (GND).
Fig. 1 Output Load Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
NOTES
V
CC
for Retention Data
V
DR
2
V
CE\ > (V
CC
- 0.2V)
V
CC
= 2V
I
CCDR
100
A
V
IN
> (V
CC
- 0.2V)
V
CC
= 3V
I
CCDR
200
A
Chip Deselect to Data
Retention Time
t
CDR
0
ns
4
Operation Recovery Time
t
R
5
ms
4, 10
Data Retention Current
CONDITIONS
167 ohms
1.73V
C=30pF
Q
C = 100pF
50 ohms
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