Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
JANUARY 2004
REV. 1.2.0
GENERAL DESCRIPTION
The XR16L580 (L580) is a 2.25 to 5.5 volt Universal
Asynchronous Receiver and Transmitter (UART) with
5 volt tolerant inputs and a reduced pin count. It is
pin-to-pin and software compatible to industry
standard 16C450, 16C550, ST16C580, ST16C650A
and XR16C850 UARTs. It has 16 bytes of TX and RX
FIFOs and is capable of operating up to serial data
rate of 1 Mbps at 2.25 volt supply voltage. The
internal registers is compatible to the 16C550
register set plus enhanced registers for additional
features to support today's high bandwidth data
communication needs. The enhanced features
include Intel or Motorola data bus interface to match
your CPU interface, automatic hardware and
software flow control to prevent data loss, selectable
RX and TX trigger levels for more efficient interrupt
service, wireless infrared (IrDA) encoder/decoder for
wireless applications and a unique Power-Save mode
to increase battery operating time. The device comes
in the 48-TQFP and a very small 32-QFN packages in
industrial temperature range.
APPLICATIONS
Handheld Terminals and Tablets
Handheld Computers
Wireless Portable Point-of-Sale Terminals
Cellular Phones DataPort
GPS Devices
Personal Digital Assistants Modules
Battery Operated Instruments
FEATURES
Industry Smallest Full Featured UART
2.25V to 5.5V Operation
5V Tolerant Inputs
Intel/Motorola Bus Select
'0 ns' Address Hold Time (T
AH
and T
ADH
)
Pin and Software Compatible to industry standard
16C450, 16C550, ST16C580, ST16C650A and
XR16C850 in the 48-TQFP package.
16-byte Transmit FIFO
16-byte Receive FIFO with Errors Flags
Selectable RX and TX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Up to 3.125 Mbps Data Rate at 5V and 2 Mbps at
3.3V and 1 Mbps at 2.25V Operation with External
Clock Input
Infrared (IrDA) Encoder/Decoder
Complete Modem Interface
Power-Save Mode to conserve battery power
Sleep Mode with Wake-up Interrupt
Small 32-QFN (5x5x0.9mm) package
Compatible to standard 48-TQFP packages
without the following redundant signals: IOR,
IOW, CS1, CS2, TXRDY#, RXRDY#, RCLK,
BAUDOUT#, OP1# and OP2#
Industrial Temperature Grade(-40 to +85
o
C)
F
IGURE
1. B
LOCK
D
IAGRAM
VCC
XTAL1
XTAL2
Crystal Osc/Buffer
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
Intel or
Motorola
Data Bus
Interface
UART
16 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
*5 V Tolerant Inputs
GNugget_BLK
A2:A0
PwrSave
16 Byte TX FIFO
RI#, CD#
RESET
(RESET#)
D7:D0
IOW# (R/W#)
CS#
INT (IRQ#)
IOR#
GND
(2.25 to 5.5 V)
16/68#
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.2.0
2
F
IGURE
2. P
ACKAGES
AND
P
IN
O
UT
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XR16L580IL
32-QFN
-40C to +85C
XR16L580IM
48-TQFP
-40C to +85C
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
13
14
1
5
1
6
17
18 1
9
20
21
2
2
2
3
24
37
38
3
9
4
0
41
42 4
3
44
45
4
6
4
7
48
48-TQFP in
Motorola Bus Mode
NC
D5
D6
D7
NC
NC
RX
TX
NC
NC
CS
#
NC
NC
NC
NC
NC
NC
GND
NC
R/W#
XTAL2
XTAL1
PwrSave
R
ESET
#
NC
DT
R#
RT
S
#
NC
IR
Q
#
NC
A0
A1
A2
NC
NC
CTS#
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
D4
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
13
14
1
5
1
6
17
18 1
9
20
21
2
2
2
3
24
37
38
3
9
4
0
41
42 4
3
44
45
4
6
4
7
48
48-TQFP in
Intel Bus Mode
NC
D5
D6
D7
NC
NC
RX
TX
NC
NC
CS
#
NC
NC
NC
NC
IOR#
GND
NC
IOW#
XTAL2
XTAL1
R
ESET
NC
DT
R#
RT
S
#
NC
IN
T
NC
A0
A1
A2
NC
CTS#
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
D4
PwrSave
16
/
6
8#
16
/
6
8#
NC
VCC
GND
NC
NC
NC
NC
NC
32
31
30
29
1 2 3 4 5 6 7 8
24 23 22 21 20 19
11
12
13
14
15
16
9
10
RI#
D6
D7
RX
TX
CS
#
XTAL1
XTAL2
IOW#
GND
IOR#
R
ESET
RTS
#
INT
DTR#
A0
A1
A2
D4
D3
D2
D1
D0
VCC
C
T
SA#
28
27
26
25
18 17
DSR#
D5
16/68#
PwrSave
NC
NC
VCC
32-pin QFN in
Intel Bus Mode
CD#
32
31
30
29
1
2
3
4
5
6
7
8
24
23
22
21
20
19
11
12
13
14
15
16
9
10
RI#
D6
D7
RX
TX
CS
#
16/68#
XTAL1
XTAL2
R/W#
GND
NC
CTS
#
R
ESET
#
RTS
#
IRQ
#
A0
A1
A2
D4
D3
D2
D1
D0
VCC
32-pin QFN in
Motorola Bus Mode
28
27
26
25
18
17
DTR#
DSR#
D5
NC
NC
PwrSave
CD#
GND
XR16L580
REV. 1.2.0
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
3
PIN DESCRIPTIONS
Pin Descriptions
N
AME
32-QFN
P
IN
#
48-TQFP
PIN#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
17
18
19
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the internal regis-
ters in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
5
4
3
1
32
31
30
29
4
3
2
47
46
45
44
43
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(NC)
14
19
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and this input
becomes read strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed by the address
lines [A2:A0], puts the data byte on the data bus to allow the host processor to
read it on the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this
input is not used.
IOW#
(R/W#)
12
16
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this input
becomes write strobe (active low). The falling edge instigates the internal write
cycle and the rising edge transfers the data byte on the data bus to an internal
register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this
input becomes read (logic 1) and write (logic 0) signal.
CS#
8
11
I
This input is chip select (active low) to enable the device.
INT
(IRQ#)
20
30
O
(OD)
When 16/68# pin is at logic 1 for Intel bus interface, this output become the active
high device interrupt output. The output state is defined by the user through the
software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a
logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes the
active low device interrupt output (open drain). An external pull-up resistor is
required for proper operation.
MODEM OR SERIAL I/O INTERFACE
TX
7
8
O
UART Transmit Data or infrared encoder data. Standard transmit and receive
interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic
1 during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for
the Infrared encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
RX
6
7
I
UART Receive Data or infrared receive data. Normal receive data input must idle
at logic 1 condition. The infrared receiver idles at logic 0.
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.2.0
4
N
OTE
: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
RTS#
21
32
O
UART Request-to-Send (active low) or general purpose output. This output must
be asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and
IER[6].
CTS#
24
38
I
UART Clear-to-Send (active low) or general purpose input. It can be used for
auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be con-
nected to VCC when not used.
DTR#
22
33
O
UART Data-Terminal-Ready (active low) or general purpose output.
DSR#
25
39
I
UART Data-Set-Ready (active low) or general purpose input. This input should
be connected to VCC when not used. This input has no effect on the UART.
CD#
26
40
I
UART Carrier-Detect (active low) or general purpose input. This input should be
connected to VCC when not used. This input has no effect on the UART.
RI#
27
41
I
UART Ring-Indicator (active low) or general purpose input. This input should be
connected to VCC when not used. This input has no effect on the UART.
ANCILLARY SIGNALS
XTAL1
10
14
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
11
15
O
Crystal or buffered clock output. This output may be use to drive a clock buffer
which can drive other device(s).
PwrSave
9
13
I
Power-Save (active high). This feature isolates the L580's data bus interface from
the host preventing other bus activities that cause higher power drain during
sleep mode. See Sleep Mode with Auto Wake-up and Power-Save Feature sec-
tion for details. This pin has an internal pull-down resistor in the 48-TQFP pack-
age. The 32-QFN package does not have this pull-down resistor.
16/68#
2
1
I
Intel or Motorola Bus Select. This pin has an internal pull-up resistor in the 48-
TQFP package. The 32-QFN package does not have this resistor.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate in the Intel
bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will operate in the
Motorola bus type of interface.
RESET
(RESET#)
23
35
I
When 16/68# pin is at logic 1 for Intel bus interface, this input becomes RESET
(active high). When 16/68# pin is at logic 0 for Motorola bus interface, this input
becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all
outputs of the UART. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset period (see
UART Reset Conditions).
VCC
28
42
Pwr 2.25V to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.
GND
13
18
Pwr Power supply common, ground.
NC
15, 16
5,6,9,10,
12,17,20-
25,29,31,
34,36,37,
48
-
No Connects. Please note that in Motorola mode, the IOR# pin becomes an NC
pin.
Pin Descriptions
N
AME
32-QFN
P
IN
#
48-TQFP
PIN#
T
YPE
D
ESCRIPTION
XR16L580
REV. 1.2.0
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
5
1.0
PRODUCT DESCRIPTION
The XR16L580 (L580) is an enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its
features set is compatible to the ST16C580 device and additionally offers Intel or Motorola data bus interface
and Power-Save to isolate the data bus interface during Sleep mode. Hence, the L580 adds 2 more inputs: 16/
68# and PwrSave pins. The XR16L580 can operate from 2.25V to 5.5V with 5 volt tolerant inputs. The
configuration registers set is 16550 UART compatible for control, status and data transfer. Also, the L580 has
16-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, transmit and receive FIFO trigger levels, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4. The L580 is fabricated
using an advanced CMOS process.
Enhanced Features
The L580 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L580 is
designed to work with low supply voltage and high performance data communication systems, that require fast
data processing time. Increased performance is realized in the L580 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the L580
provides the Power-Save mode that drastically reduces the power consumption when the device is not used.
The combination of the above greatly reduces the CPU's bandwidth requirement, increases performance, and
reduces power consumption.
Data Bus Interface, Intel or Motorola Type
The L580 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface.
The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#,
IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#
and CS# signals for data bus transactions. See pin description section for details on all the control signals. The
Intel and Motorola bus interface selection is made through the pin, 16/68#.
Data Rate
The L580 is capable of operation up to 3.125 Mbps at 5V, 2 Mbps at 3.3V and 1 Mbps at 2.5V supply with 16X
internal sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and
XTAL2, or external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz, all
standard data rates of up to 921.6 kbps can be generated.
Internal Enhanced Register Sets
The L580 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, infrared encoder/decoder enable/disable,
modem interface controls and status, sleep mode and Power-Save mode are all standard features. Following a
power on reset or an external reset (and operating in 16 or Intel Mode), the registers defaults to the reset
condition and its is compatible with previous generation of UARTs, 16C450, 16C550, 16C580, 16C650A and
16C850.
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