XR-215A
...the analog plus company
TM
Monolithic
PhaseLocked Loop
Rev. 1.01
E
1996
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
(510) 668-7010
1
June 1997-3
FEATURES
D
Wide Frequency Range: 0.5Hz to 25MHz
D
Wide Supply Voltage Range: 5V to 26V
D
Wide Dynamic Range: 300
m
V to 3V, nominally
D
ON-OFF Keying and Sweep Capability
D
Wide Tracking Range: Adjustable from +1% to
+50%
D
High-Quality FM Detection: Distortion 0.15%
Signal/Noise 65dB
APPLICATIONS
D
FM Demodulation
D
Frequency Synthesis
D
FSK Coding/Decoding (MODEM)
D
Tracking Filters
D
Signal Conditioning
D
Tone Decoding
D
Data Synchronization
D
Telemetry Coding/Decoding
D
FM, FSK and Sweep Generation
D
Crystal-Controlled PLL
D
Wideband Frequency Discrimination
D
Voltage-to-Frequency Conversion
GENERAL DESCRIPTION
The XR-215A is a highly versatile monolithic phase-
locked loop (PLL) system designed for a wide variety of
applications in both analog and digital communication
systems. It is especially well suited for FM or FSK
demodulation, frequency synthesis and tracking filter
applications. The XR-215A can operate over a large
choice of power supply voltages ranging from 5V to 26V
and a wide frequency band of 0.5Hz to 25MHz. It can
accommodate analog signals between 300mV and 3V.
ORDERING INFORMATION
Part No.
Package
Operating Temperature
Range
XR-215ACP
16 Lead 300 Mil PDIP
0
C to 70
C
XR-215ACD
16 Lead SOIC (Jedec, 0.300")
0
C to 70
C
XR-215A
2
Rev. 1.01
9
V
EE
16
V
CC
4
PHCP1
6
PHCP2
1
OPAMP
7
COMP
Phase
Comparator
Op
Amp
2
PCO1
3
PCO2
8
OPAMPO
15
VCOO
VCO
5
BIAS
12
VSI
11
VGC
10
RGS
14
TCI2
13
TCI1
Figure 1. XR-215A Block Diagram
XR-215A
3
Rev. 1.01
PIN CONFIGURATION
16 Lead 300 Mil PDIP
V
CC
VCOO
TCI2
TCI1
VSI
VGC
RGS
V
EE
OPAMP
PCO1
PCO2
PHCP1
BIAS
PHCP2
COMP
OPAMPO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
VCOO
TCI2
TCI1
VSI
VGC
RGS
V
EE
OPAMP
PCO1
PCO2
PHCP1
BIAS
PHCP2
COMP
OPAMPO
16 Lead SOIC (Jedec, 0.300")
16
1
9
8
2
3
4
5
6
7
15
14
13
12
11
10
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
OPAMP
I
Operational Amplifier Input.
2
PCO1
O
Phase Comparator Output 1.
3
PCO2
O
Phase Comparator Output 2.
4
PHCP1
I
Phase Comparator Input 1.
5
BIAS
I
Phase Comparator Bias Input.
6
PHCP2
I
Phase Comparator Input 2.
7
COMP
I
Operational Amplifier Frequency Compensation Input.
8
OPAMPO
O
Operational Amplifier Output.
9
V
EE
-
Negative Power Supply.
10
RGS
I
Range Select Input.
11
VGC
I
VCO Gain Control.
12
VSI
I
VCO Sweep Voltage Input.
13
TCI1
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
14
TCI2
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
15
VCOO
O
VCO Output.
16
V
CC
-
Positive Power Supply.
XR-215A
4
Rev. 1.01
DC ELECTRICAL CHARACTERISTICS
Test Conditions: V
CC
= 12V (single supply), T
A
= 25
C, Test Circuit of
Figure 3 with C
0
= 100 pF,
(silver-mica) S
1
,S
2
, S
5
, closed, S
3
, S
4
open unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit.
Conditions
GENERAL CHARACTERISTICS
Supply Voltage
Single Supply
5
26
V
Figure 3
Split Supply
+2.5
+13
V
Figure 4
Supply Current
8
11
15
mA
Figure 3
Upper Frequency Limit
20
25
MHz
Figure 3, S
1
Open, S
4
Closed
Lowest Practical Operating
Frequency
0.5
Hz
C
0
= 500
m
F (Non-Polarized)
VCO Section
Stability:
Temperature
250
600
ppm/
C
See
Figure 7, 0
C
T
T
< 70
C
Power Supply
0.1
%/V
V
CC
> 10V
Sweep Range
5:1
8:1
S
3
Closed, S
4
Open, 0 < V
S
< 6V
See
Figure 10, C
0
= 2000pF
Output Voltage Swing
1.5
2.5
Vp-p
S
5
Open
Rise Time
20
ns
Fall Time
30
ns
10pF to Ground at Pin 15
Phase Comparator Section
Conversion Gain
2
V/rad
V
IN
> 50mV rms (See Characteristic Curves)
Output Impedance
6
k
W
Measured Looking into Pins 2 or 3
Output Offset Voltage
20
100
mV
Measured Across Pins 2 and 3
V
IN
= 0, S
5
Open
OP AMP Section
Open Loop Voltage Gain
66
80
dB
S
2
Open
Slew Rate
2.5
V/
m
sec
A
V
= 1
Input Impedance
0.5
2
M
W
Output Impedance
2
k
W
Output Swing
7
10
Vp-p
R
L
= 30k
W
From Pin 8 to Ground
Input Offset Voltage
1
10
mV
Input Bias Current
80
nA
Common Mode Rejection
90
dB
Note:
Bold face parameters are covered by production test and guaranteed over operating temperature range.
XR-215A
5
Rev. 1.01
DC ELECTRICAL CHARACTERISTICS
(CONT'D)
Parameter
Min.
Typ.
Max.
Unit
Conditions
SPECIAL APPLICATIONS
A) FM Demodulation
Test Conditions: Test circuit of
Figure 5, V
CC
= 12V, input signal = 10.7MHz FM with
D
f = 75kHz. f
mod
= 1kHz.
Detection Threshold
0.8
3
mV rms
50
W
source
Demodulated Output Amplitude
500
mV rms
Measured at Pin 8
Distortion (THD)
0.15
0.5
%
AM Rejection
40
dB
V
IN
= 10mV rms, 30% AM
Output Signal/Noise
65
dB
B) Tracking Filter
Test Conditions: Test circuit of
Figure 6, V
CC
= 12V, f
o
= 1 MHz, V
IN
= 100mV rms, 50
W
source.
Tracking Range (% of f
o
)
+50
See
Figure 5 and Figure 25
Discriminator Output
D
V
OUT
D
f / f
o
50
mV/%
Adjustable - See Applications Information
Note:
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply
26 volts
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation (Package Limitation)
Plastic Package
625mW
. . . . . . . . . . . . . . . . . . . . . . . .
Derate above 25
C
5mW/
C
. . . . . . . . . . . . . . . . . . . .
SOIC Package
500mW
. . . . . . . . . . . . . . . . . . . . . . . . .
Derate above 25
C 4mW/
C
. . . . . . . . . . . . . . . . . . . .
Temperature
Storage
-65
C to +150
C
. . . . . . . . . . . . . . . . . . . . . . .
XR-215A
6
Rev. 1.01
6
Figure 2. Equivalent Schematic Diagram
1
16
2
3
5
4
11
14 13
15
12
7
8
9
10
SYSTEM DESCRIPTION
The XR-215A monolithic PLL system consists of a
balanced phase comparator, a highly stable voltage-
controlled oscillator (VCO) and a high speed operational
amplifier. The phase comparator outputs are internally
connected to the VCO inputs and to the noninverting input
of the operational amplifier. A self-contained PLL System
is formed by simply AC coupling the VCO output to either
of the phase comparator inputs and adding a low-pass
filter to the phase comparator output terminals.
The VCO section has frequency sweep, on-off keying,
sync, and digital programming capabilities. Its frequency
is highly stable and is determined by a single external
capacitor. The operational amplifier can be used for audio
preamplification in FM detector applications or as a high
speed sense amplifier (or comparator) in FSK
demodulation.
DESCRIPTION OF CIRCUIT CONTROLS
Phase Comparator Inputs (Pins 4 and 6)
One input to the phase comparator is used as the signal
input. The remaining input should be AC coupled to the
VCO output (pin 15) to complete the PLL (see
Figure 3).
For split supply operation, these inputs are biased from
ground as shown in
Figure 4. For single supply operation,
a resistive bias string similar to that shown in
Figure 3
should be used to set the bias level at approximately
V
CC
/2. The DC bias current at these terminals is
nominally 8
m
A.
Phase Comparator Bias (Pin 5)
This terminal should be DC biased as shown in
Figure 3
and
Figure 4, and AC grounded with a bypass capacitor.
Phase Comparator Outputs (Pins 2 and 3)
The low frequency (or DC) voltage across these pins
corresponds to the phase difference between the two
signals at the phase comparator inputs (pins 4 and 6). The
phase comparator outputs are internally connected to the
VCO control terminals (see
Figure 2.) One of the outputs
(pin 3) is internally connected to the noninverting input of
the operational amplifier. The low-pass filter is achieved
by connecting an RC network to the phase comparator
outputs as shown in
Figure 15.
XR-215A
7
Rev. 1.01
16 V
CC
Figure 3. Test Circuit for Single Supply Operation
+12V
0.1
m
F
0.1
m
F
5K
5K
Signal
Input
Sweep
Input
V
s
U1
XR-215A
S
3
1K
5K
0.1
m
F
2K
2K
0.1
m
F
S
5
VCO
Output
0.068
m
F
Demodulated
Output
10K
S
2
300pF
R
F
100K
R
P
10K
10K
750
5pF
S
1
100pF
S
4
2nF
2nF
50
50
Phase
Comp.
VCO
6
11
12
10
9 13
14
2
3 1
7
8
15
4
5
V
EE
Op
Amp
XR-215A
8
Rev. 1.01
16
V
CC
13
Op
Amp
Figure 4. Test Circuit for Split-Supply Operation
0.1
m
F
+6V
0.1
m
F
U1
XR-215A
5K
0.1
m
F
2K
Signal
Input
50
W
2K
0.1
m
F
2K
VCO
Output
Demodulated
Output
100pF
10K
10K
300pF
R
F
100K
R
P
10K
-6V
750
S
4
-6V
2nF
2nF
50
50
Phase
Comp.
VCO
11
12
10
9
14
3 1
7
15
4
8
6
2
V
EE
5
0.068
m
F
XR-215A
9
Rev. 1.01
16 V
CC
Figure 5. Test Circuit for FM Demodulation
0.1
m
F
0.1
m
F
+12V
U1
XR-215A
0.1
m
F
2K
3K
FM Input
(50
W
Source)
2K
1K
0.1
m
F
VCO
Output
10K
Demodulated
Output
10nF
300pF
R
F
100K
R
P
10K
7.5K
30pF
750
50
50
1nF
1nF
Phase
Comp.
6
11
12
10
V
EE
VCO
13
9
14
3 1
7
2
Op
Amp
5
4
15
8
XR-215A
10
Rev. 1.01
16 V
CC
Figure 6. Test Circuit For Tracking Filter
+12V
5K
5K
0.1
m
F
Signal
Input
50
W
R
0
2K
U1
XR-215A
0.1
m
F
2K
0.1
m
F
2K
0.1
m
F
10K
Demodulated
Output
VCO
Output
1K
R
F
40K
300pF
C
0
200pF
50
50
R
P
20K
5nF
5nF
6
11
12
10
9
13
14
2
3 1
7
Phase
Comp.
VCO
8
4
5
Op
Amp
15
V
EE
XR-215A
11
Rev. 1.01
Figure 7. Typical VCO Temperature Coefficient Range as a
Function of Operating Frequency (Pin 10 open)
-800
-400
0
400
800
10KHz
100KHz
1MHz
10MHz
VCO Frequency (Hz)
V
CC
= 12V
R
0
= 5k
W
VCO
T
emperature Coefficient (PPM/ C)
Figure 8. VCO Free Running Frequency vs. Timing Capacitor
Rx=750
W
Between Pins 9 & 10
Pin 10 Open
10
7
10
2
10
3
10
4
10
5
10
6
10
10
7
10
6
10
5
10
4
10
3
10
2
VCO Frequency (Hz)
T
iming Capacitance C (pF)
0
XR-215A
12
Rev. 1.01
VCO Timing Capacitor (Pins 13 and 14)
The VCO free-running frequency, f
o
, is inversely proportional to timing capacitor C
0
connected between pins 13 and 14.
(See
Figure 8.)
VCO Output (Pin 15)
The VCO produces approximately a 2.5Vp-p output signal at this pin. The DC output level is approximately 2 volts below
V
CC
. This pin should be connected to pin 9 through a 10k
W
resistor to increase the output current drive capability. For
high voltage operation (V
CC
> 20V), a 20k
W
resistor is recommended. It is also advisable to connect a 500
W
resistor in
series with this output for short circuit protection.
0.1
1
10
100
1000
High Level Input
Constant = 1V rms
2V/RAD
Low Level Input Input Amplitude (mV rms)
1.0
0.1
0.01
Figure 9. Phase Comparator Conversion Gain, K
d
, versus Input Amplitude
Phase Comparator Conversion Gain K
d
XR-215A
13
Rev. 1.01
Figure 10. Typical Frequency Sweep Characteristics as a
Function of Applied Sweep Voltage
R
X
=
1
R
X
=750
W
Bias Pins 1,4,5,6 to V
CC
/2
5
4
3
2
1
+2
0
-2
-4
-6
-8
-10
-12
Co
2K
Vs
VCO
2K
Rx
V
CC
OUTPUT
Fo
12
11
16 14
13
15
10
9
R
s
Net Applied Sweep Voltage V
S
- V
SO
(Volts)
Normalized Frequency (f/fo)
Note:
V
SO
V
CC
- 5V = Open Circuit Voltage at pin 12
XR-215A
14
Rev. 1.01
Figure 11. XR-215A Op Amp Frequency Response
8
V
out
0.1
m
F
1
R
s
1K
V
in
3
C
c
Open Loop Response
A
V
= 100
R
F
= 100K
A
V
= 1000
R
F
= 1M
A
V
= 10
C
C
= 50pF; R
F
= 10K
A
V
= 1
C
C
= 300pF; R
F
= 1K
100
80
60
40
20
0
-20
100H
1KHz
10KHz
100KHz
1MHz
10MHz
R
F
V
oltage Gain (dB)
Frequency
VCO Sweep Input (Pin 12)
The VCO Frequency can be swept over a broad range by applying an analog sweep voltage, V
S
, to pin 12 (see
Figure 10.) The impedance looking into the sweep input is approximately 50
W
. Therefore, for sweep applications, a
current limiting resistor, R
S
, should be connected in series with this terminal. Typical sweep characteristics of the circuit
are shown in
Figure 10. The VCO temperature dependence is minimum when the sweep input is not used.
CAUTION: For safe operation of the circuit, the maximum current, I
S
, drawn from the sweep terminal should be limited to
5mA or less under all operating conditions.
ON-OFF KEYING: With pin 10 open circuited, the VCO can be keyed off by applying a positive voltage pulse to the
sweep input terminal. With R
S
= 2k
W
, oscillations will stop if the applied potential at pin 12 is raised 3 volts above its
open-circuit value. When sweep, sync, or on-off keying functions are not used, R
S
is not necessary.
XR-215A
15
Rev. 1.01
Figure 12. Explanation of VCO Range-Select Controls
Range Select
> 3V, F
1
Internal
Bias
I
1
I
2
T
1
T
2
600
1.3V
10
R
X
Input
0V, Fo
9
Fo = F1(1+(0.6/R
X
))
Range-Select (Pin 10)
The frequency range of the XR-215A can be extended by
connecting an external resistor, R
X
, between pins 9 and
10. With reference to
Figure 12, the operation of the
range-select terminal can be explained as follows: The
VCO frequency is proportional to the sum of currents I
1
and I
2
through transistors T
1
and T
2
on the monolithic
chip. These transistors are biased from a fixed internal
reference. The current I
1
is set internally, whereas I
2
is set
by the external resistor R
X
. Thus, at any C
0
setting, the
VCO frequency can be expressed as:
f
0
+
f
1
1
)
0.6
R
X
where f
1
is the frequency with pin 10 open circuited and
R
X
is in k
W
. External resistor R
X
(
750
W
) is
recommended for operation at frequencies in excess of
5MHz.
The range select terminal can also be used for fine tuning
the VCO frequency, by varying the value of R
X
. Similarly,
the VCO frequency can be changed in discrete steps by
switching in different values of R
X
between pins 9 and 10.
Digital Programming
Using the range select control, the VCO frequency can be
stepped in a binary manner, by applying a logic signal to
pin 10, as shown in
Figure 12. For high level logic inputs,
transistor T
2
is turned off, and R
X
is effectively switched
out of the circuit. Using the digital programming capability,
the XR-215A can be time-multiplexed between two
separate input frequencies, as shown in
Figure 19 and
Figure 20.
Amplifier Input (Pin 1)
This pin provides the inverting input for the operational
amplifier section. Normally it is connected to pin 2 through
a 10 k
W
external resistor (see
Figure 3 or Figure 4.)
XR-215A
16
Rev. 1.01
Amplifier Output (Pin 8)
This pin is used as the output terminal for FM or FSK
demodulation. The amplifier gain is determined by the
external feedback resistor, R
F
, connected between pins 1
and 8. Frequency response characteristics of the
amplifier section are shown in
Figure 11.
Amplifier Compensation (Pin 7)
The operational amplifier can be compensated for unity
gain by a single 300pF capacitor from pin 7 to ground.
(See
Figure 11.)
BASIC PHASE-LOCKED LOOP OPERATION
Principle of Operation
The phase-locked loop (PLL) is a unique and versatile
circuit technique which provides frequency selective
tuning and filtering without the need for coils or inductors.
As shown in
Figure 13, the PLL is a feedback system
comprised of three basic functional blocks: phase
comparator, low-pass filter and voltage-controlled
oscillator (VCO). The basic principle of operation of a PLL
can be briefly explained as follows: with no input signal
applied to the system, the error voltage V
d
, is equal to
zero. The VCO operates at a set frequency, f
o
, which is
known as the "free-running" frequency. If an input signal is
applied to the system, the phase comparator compares
the phase and frequency of the input signal with the VCO
frequency and generates an error voltage, V
e
(t), that is
related to the phase and frequency difference between
the two signals. This error voltage is then filtered and
applied to the control terminal of the VCO. If the input
frequency, fs, is sufficiently close to f
o
, the feedback
nature of the PLL causes the VCO to synchronize or "lock"
with the incoming signal. Once in lock, the VCO frequency
is identical to the input signal, except for a finite phase
difference.
A Linearized Model for PLL
When the PLL is in lock, it can be approximated by the
linear feedback system shown in
Figure 14.
O
s
and
O
o
are
the respective phase angles associated with the input
signal and the VCO output, F(s) is the low-pass filter
response in frequency domain, and K
d
and K
o
are the
conversion gains associated with the phase comparator
and VCO sections of the PLL.
DEFINITION OF XR-215A PARAMETERS USED FOR
PLL APPLICATIONS DESIGN
VCO Free-Running Frequency, f
o
The VCO frequency with no input signal is determined by
selection of C
0
across pins 13 and 14 and can be
increased by connecting an external resistor R
X
between
pins 9 and 10. It can be approximated as:
f
0
[
220
C
0
1
)
0.6
R
X
where C
0
is in
m
F and R
X
is in k
W
. (See
Figure 8.)
Figure 13. Block Diagram of a Phase-Locked Loop
f
s
Input
Signal
V
S
(t)
Phase
Comparator
Lowpass
Filter
VCO
V
e
(t)
V
d
(t)
V
d
(t)
f
o
V
O
(t)
XR-215A
17
Rev. 1.01
Figure 14. Linearized Model of a PLL as a
Negative Feedback System
F(s)
K
d
O
0
O
s
Ko
s
-
Phase Comparator Gain K
d
The output voltage from the phase comparator per radian
of phase difference at the phase comparator inputs (pins
4 and 6). The units are volts/radians. (See
Figure 9.)
VCO Conversion Gain Ko
The VCO voltage-to-frequency conversion gain is
determined by the choice of timing capacitor C
0
and gain
control resistor, R
0
connected externally across pins 11
and 12. It can be expressed as:
700
C
0
R
0
K
0
[
(radians/sec/volt)
where C
0
is in
m
F and R
0
is in k
W
. For most applications,
recommended values for R
0
range from 1k
W
to 10k
W
.
Lock Range (
D
wL)
The range of frequencies in the vicinity of f
o
, over which
the PLL can maintain lock with an input signal. It is also
known as the "tracking" or "holding" range. If saturation or
limiting does not occur, the lock range is equal to the loop
gain, i.e.
Dw
L
= K
T
= K
d
K
o
.
Capture Range (
D
wC)
The band of frequencies in the vicinity of f
o
where the PLL
can establish or acquire lock with an input signal. It is also
known as the "acquisition" range. It is always smaller than
the lock range and is related to the low-pass filter
bandwidth. It can be approximated by a parametric
equation of the form:
Dw
C
Dw
L
|F(j
Dw
C
)|
where |F(j
Dw
C
| is the low-pass filter magnitude response
at
w
=
Dw
C
. For a simple lag filter, it can be expressed as:
Dw
L
T
1
Dw
C
[
where T
1
is the filter time constant.
Amplifier Gain AV
The voltage gain of the amplifier section is determined by
feedback resistors R
F
and Rp between pins (8,1) and
(2,1) respectively. (See
Figure 3 and Figure 4.) It is given
by:
R
F
R
1
)
R
P
A
V
[
where R
1
is the (6k
W
) internal impedance at pin 2.
XR-215A
18
Rev. 1.01
Low-Pass Filter
The low-pass filter section is formed by connecting an
external capacitor or RC network across terminals 2 and
3. The low-pass filter components can be connected
either between pins 2 and 3 or, from each pin to ground.
Typical filter configurations and corresponding filter
transfer functions are shown in
Figure 15 where R
1
(6k
W
)
is the internal impedance at pins 2 and 3. It should be
noted that the rejection of the low pass filter decreases
above 2MHz when the capacitor is tied from pin 2 to 3.
Figure 15.
2
3
R
2
C
1
Lag Lead Filter
2
3
C
1
C
1
R
2
R
2
t
1
= 2R
1
C
1
C
1
2
3
C
1
C
1
2
3
t
1
= 2R
1
C
1
Lag Filter
1
S
t
1
F(s)
=
F(s)
=
F(s)
=
t
1
= R
1
C
1
1 + S
t
2
1 + S(
t
1
+
t
2
)
1 + S
t
2
1 + S(
t
1
+
t
2
)
t
1
= R
1
C
1
1
S
t
1
F(s)
=
t
2
= R
2
C
1
t
2
= R
2
C
1
Note:
R
1
= 6k
W
internal resistor.
The natural frequency
w
n
can be calculated from the VCO conversion gain K
0
, the phase comparator conversion gain
K
d
, and the low pass filter time constants
t
1
and
t
2
as follows:
t
2
)
1
K
0
K
d
j + w
n
2
Then the damping factor
j
can be calculated using:
w
n
+
K
0
K
d
t
1
) t
2
XR-215A
19
Rev. 1.01
16 V
CC
Figure 16. Circuit Connection for FM Demodulation
+12V
5K
5K
FM
Input
U1
XR-215A
2K
0.1
m
F
Cc
R
0
0.1
m
F
2K
Cc
300pF
Demodulated
Output
2K
8K
7.5K
R
F
Volume
Control
10nF (De-Emphasis)
C
0
R
x
50
C
1
50
C
1
R
P
10K
Cc Coupling Capacitor
Phase
Comp.
5
Op
Amp
8
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
APPLICATIONS INFORMATION
FM Demodulation
Figure 16 shows the external circuit connections to the XR-215A for frequency-selective FM demodulation. The choice
of C
0
is determined by the FM carrier frequency (see
Figure 8.) The low-pass filter capacitor C
1
is determined by the
selectivity requirements. For carrier frequencies of 1 to 10MHz, C
1
is in the range of 10
C
0
to 30
C
0
. The feedback
resistor R
F
can be used as a "volume-control" adjustment to set the amplitude of the demodulated output. The
demodulated output amplitude is proportional to the FM deviation and to resistors R
0
and R
F
for +1% FM deviation it can
be approximated as:
V
OUT
[
R
0
R
F
1
)
0.6
R
X
mV, rms
where all resistors are in k
W
and R
X
is the range extension resistor connected across pins 9 and 10. For circuit operation
below 5MHz, R
X
can be omitted. For operation above 5MHz, R
X
750
W
is recommended.
Typical output signal/noise ratio and harmonic distortion are shown in
Figure 17 and Figure 18 as a function of FM
deviation, for the component values shown in
Figure 5.
XR-215A
20
Rev. 1.01
Multi-Channel Demodulation
The AC digital programming capability of the XR-215A allows a single circuit be time-shared or multiplexed between two
information channels, and thereby selectively demodulate two separate carrier frequencies.
Figure 19 shows a
practical circuit configuration for time-multiplexing the XR-215A between two FM channels, at 1MHz and 1.1MHz
respectively. The channel-select logic signal is applied to pin 10, as shown in
Figure 19 with both input channels
simultaneously present at the PLL input (pin 4).
Figure 20 shows the demodulated output as a function of the
channel-select pulse where the two inputs have sinusoidal and triangular FM modulation respectively.
Figure 17. Output Signal/Noise Ratio as a Function of FM Deviation
f
o
=10 MHz
f
mod
= 1 KHz
V
IN
= 20 mV rms
(Test Circuit of
Figure 5)
100
80
60
40
0.01%
0.1%
1.0%
100%
10%
Frequency Deviation
D
f/f
o
Figure 18. Output Distortion as a Function of FM Deviation
1%
0.5%
0
0.01%
0.1%
1.0%
100%
10%
f
o
=10MHz
f
mod
= 1KHz
V
IN
= 20 mV rms
V
OUT
= Constant @ 2 V
PP
(Test Circuit of
Figure 5)
Demodulated Output Signal / Noise (dB)
Frequency Deviation
D
f/f
o
Distortion (THD)
XR-215A
21
Rev. 1.01
V
CC
16
Figure 19. Time-Multiplexing XR-215A Between Two Simultaneous FM Channels
U1
XR-215A
Channel 2
F
2
=1.1MHz
Channel 1
F
1
=1MHz
1K
0.1
m
F
0.1
m
F
+5V
1K
Demodulated
Output
10nF
(De-Emphasis)
7.5K
10nF
10nF
-5V
10K
300pF
300pF
Co
100K
3K
Co
220pF
R
0
3K
R
x
6K
1K
Channel
Select
-5V
0V F
o
=F
1
-5V F
o
=F
2
10K
R
P
10K
C
c
Coupling Capacitor
4nF
4nF
Phase
Comp.
5
Op
Amp
8
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
VCO
XR-215A
22
Rev. 1.01
Figure 20. Demodulated Output Waveforms for Time-Multiplexed Operation
Demodulated Output
Channel Select Pulse
FSK Demodulation
Figure 21 contains a typical circuit connection for FSK
demodulation. When the input frequency is shifted,
corresponding to a data bit, the DC voltage at the phase
comparator outputs (pins 2 and 3) also reverses polarity.
The operational amplifier section is connected as a
comparator, and converts the DC level shift to a binary
output pulse. One of the phase comparator outputs (pin 3)
is AC grounded and serves as the bias reference for the
operational amplifier section. Capacitor C
1
serves as the
PLL loop filter, and C
2
and C
3
as post-detection filters.
Range select resistor, R
X
, can be used as a fine-tune
adjustment to set the VCO frequency.
Typical component values for 300 baud and 1200 baud
operation are listed below:
Operating
Conditions
Typical Component
Values
300 Baud
Low Band: f
1
= 1070Hz
f
2
= 1270Hz
High Band: f
1
= 2025Hz
f
2
= 2225Hz
R
0
= 5k
W
, C
0
= 0.17
m
F
C
1
= C
2
= 0.047
m
F,
C
3
= 0.033
m
F
R
0
= 8k
W
, C
0
= 0.1
m
F
C
1
= C
2
= C
3
= 0.033
m
F
1200 Baud
f
1
= 1200Hz
f
2
= 2200Hz
R
0
= 2k
W
, C
0
= 0.12
m
F
C
1
= C
3
= 0.003
m
F
C
2
=
0.01
m
F
Table 1. Typical Component Values for Modems
Note:
For 300 Baud operation the circuit can be time-multiplexed be-
tween high and low bands by switching the external resistor R
X
in and out of the circuit with a control signal, as shown in
Figure 12.
FSK Generation
The digital programming capability of the XR-215A can be
used for FSK generation. A typical circuit connection for
this application is shown in
Figure 22. The VCO
frequency can be shifted between the mark (f
2
) and space
(f
1
) frequencies by applying a logic pulse to pin 10. The
circuit can provide two separate FSK outputs: a low level
(2.5 Vp-p) output at pin 15 or a high amplitude (10 Vp-p)
output at pin 8. The output at each of these terminals is a
symmetrical squarewave with a typical second harmonic
content of less than 0.3%.
XR-215A
23
Rev. 1.01
16
V
CC
Figure 21. Circuit Connection for FSK Demodulation
0.1
m
F
+12V
5K
5K
U1
XR-215A
2K
FSK Input
R
o
2K
0.1
m
F
0.1
m
F
10K
V
OUT
10V
pp
8K
1
m
F
10K
10K
2K
C
0
R
X
5K
C
1
C
2
C
3
0.1
m
F
Phase
Comp.
VCO
5
8
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
Op
Amp
XR-215A
24
Rev. 1.01
8
16 V
CC
Figure 22. Circuit Connection For FSK Generation
U1
XR-215A
0.1
m
F
0.1
m
F
+12V
5K
5K
FSK Output
(Low Level)
2.5V
PP
F1
F2
FSK Output
10K
C
0
5K
R
x
Keying
Input
+5V
0V
0.1
m
F
3K
10K
10V
PP
F1
F2
Phase
Comp.
5
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
VCO
Op
Amp
Frequency Synthesis
In frequency synthesis applications, a programmable counter or divide-by-N circuit is connected between the VCO
output (pin 15) and one of the phase detector inputs (pins 4 or 6), as shown in
Figure 23. The principle of operation of the
circuit can be briefly explained as follows: The counter divides down the oscillator frequency by the programmable
divider modulus, N. Thus, when the entire system is phase-locked to an input signal at frequency, f
s
, the oscillator output
at pin 15 is at a frequency (Nf
s
), where N is the divider modulus. By proper choice of the divider modulus, a large number
of discrete frequencies can be synthesized from a given reference frequency. The low-pass filter capacitor C
1
is
normally chosen to provide a cut-off frequency equal to 0.1% to 2% of the signal frequency, f
s
.
XR-215A
25
Rev. 1.01
16 V
CC
Op
Amp
Figure 23. Circuit Connection For Frequency Synthesis
C
c
0.1
m
F
+5V
N
10K
Cc
Level
Shifter
VCO Output
Fo=NFs
20K
Input
F=Fs
Cc
U1
XR-215A
Rx
4K
1K
Binary
Range Select
(Optional)
20K
-5V
C
0
20K
C
1
SN7493 or Equivalent
Phase
Comp.
VCO
5
8
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
C
1
The circuit was designed to operate with commercially available monolithic programmable counter circuits using TTL
logic, such as MC4016, SN5493 or equivalent. The digital or analog tuning characteristics of the VCO can be used to
extend the available range of frequencies of the system, for a given setting of the timing capacitor C
0
.
Typical input and output waveforms for N = 16 operation with f
s
= 100kHz and f
o
= 1.6MHz are shown in
Figure 24.
Figure 24. Typical Input/Output Waveforms for N=16
Top: Input (100kHz)
Bottom: VCO Output (1.6MHz)
XR-215A
26
Rev. 1.01
Tracking Filter/Discriminator
The wide tracking range of the XR-215A allows the
system to track an input signal over a 3:1 frequency
range, centered about the VCO free running frequency.
The tracking range is maximum when the binary range-
select (pin 10) is open circuited. The circuit connections
for this application are shown in
Figure 25. Typical
tracking range for a given input signal amplitude is shown
in
Figure 26. Recommended values of external
components are:
1k
W
< R
0
< 4k
W
and 30 C
0
< C
1
< 300 C
0
where the timing
capacitor C
0
is determined by the center frequency
requirements (see
Figure 8.)
16 V
CC
Figure 25. Circuit Connection For Tracking Filter Applications
+12V
0.1
m
F
5K
5K
U1
XR-215A
0.1
m
F
Signal
Input
Vs
Ro
2K
2K
0.1
m
F
2K
Cc
10K
VCO
Output
10K
Discriminator
Output
300pF
C
0
R
F
R
P
20K
C
1
C
1
50
50
Phase
Comp.
Op
Amp.
5
8
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
VCO
XR-215A
27
Rev. 1.01
The phase-comparator output voltage is a linear measure of the VCO frequency deviation from its free-running value.
The amplifier section, therefore, can be used to provide a filtered and amplified version of the loop error voltage. In this
case, the DC output level at pin 15 can be adjusted to be directly proportional to the difference between the VCO
free-running frequency, fo, and the input signal, fs. The entire system can operate as a "linear discriminator" or analog
"frequency-meter" over a 3:1 change of input frequency. The discriminator gain can be adjusted by proper choice of R
0
or R
F
, for the test circuit of
Figure 25, the discriminator output is approximately (0.7 R
0
R
F
) mV per % of frequency
deviation where R
0
and R
F
are in k
W
. Output non-linearity is typically less than 1% for frequency deviations up to +15%.
Figure 28 shows the normalized output characteristics as a function of input frequency, with R
0
= 2k
W
and R
F
= 36k
W
.
Crystal-Controlled PLL
The XR-215A can be operated as a crystal-controlled phase-locked loop by replacing the timing capacitor with a crystal.
A circuit connection for this application is shown in
Figure 28. Normally a small tuning capacitor (
30pF) is required in
series with the crystal to set the crystal frequency. For this application the crystal should be operated in its fundamental
mode. Typical pull-in range of the circuits is +1kHz at 10MHz. There is some distortion on the demodulated output.
Figure 26. Tracking Range vs. Input Amplitude
(Pin 10 Open Circuited)
Tracking Range
Normalized Temperature Range (f/f
o
)
0.5
1.0
2.0
1.0
10
100
1000
R
0
= 2k
W
Signal Input (mV rms)
XR-215A
28
Rev. 1.01
Figure 27. Typical Discriminator Output Characteristics for Tracking Filter Applications
Normalized Tracking Range (f/f
o
)
Slope = 50mV Per %
+3
+2
+1
0
-1
-2
-3
0.4
0.6
0.8
1.0
1.2
1.4
1.6
R
0
= 2K
W
R
F
= 36K
W
V
IN
= 50mV rms
Change of
Frequency
Normalized Output (V
olts)
16 V
CC
Figure 28. Typical Circuit Connection for Crystal-Controlled PLL.
+12V
0.1
m
F
0.1
m
F
5K
5K
Signal
Input
Vs
0.01
m
F
U1
XR-215A
20K
16K
VCO
Output
0.01
m
F
10K
Demodulated
Ouput
10nF
100K
300pF
30pF
10MHz
Crystal
Fundamental
Mode
10K
10nF
10nF
1K
50
50
VCO
Phase
Comp.
Op
Amp.
5
8
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
XR-215A
29
Rev. 1.01
16 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
16
1
9
8
D
e
B
1
A
1
E
1
E
A
L
B
Seating
Plane
SYMBOL
MIN
MAX
MIN
MAX
INCHES
A
0.145
0.210
3.68
5.33
A
1
0.015
0.070
0.38
1.78
A
2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B
1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
0.745
0.840
18.92
21.34
E
0.300
0.325
7.62
8.26
E
1
0.240
0.280
6.10
7.11
e
0.100 BSC
2.54 BSC
e
A
0.300 BSC
7.62 BSC
e
B
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
4.06
0
15
0
15
MILLIMETERS
A
2
C
Note: The control dimension is the inch column
e
B
e
A
XR-215A
30
Rev. 1.01
SYMBOL
MIN
MAX
MIN
MAX
A
0.093
0.104
2.35
2.65
A
1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.009
0.013
0.23
0.32
D
0.398
0.413
10.10
10.50
E
0.291
0.299
7.40
7.60
e
0.050 BSC
1.27 BSC
H
0.394
0.419
10.00
10.65
L
0.016
0.050
0.40
1.27
0
8
0
8
INCHES
MILLIMETERS
16 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
Rev. 1.00
e
16
9
8
D
E
H
B
A
L
C
A
1
Seating
Plane
Note: The control dimension is the millimeter column
1
XR-215A
31
Rev. 1.01
Notes
XR-215A
32
Rev. 1.01
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1975 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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