XR-2211
...the analog plus company
TM
FSK Demodulator/
Tone Decoder
Rev. 3.01
E
1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
FAX (510) 668-7017
1
June 1997-3
FEATURES
D
Wide Frequency Range, 0.01Hz to 300kHz
D
Wide Supply Voltage Range, 4.5V to 20V
D
HCMOS/TTL/Logic Compatibility
D
FSK Demodulation, with Carrier Detection
D
Wide Dynamic Range, 10mV to 3V rms
D
Adjustable Tracking Range, +1% to 80%
D
Excellent Temp. Stability, +50ppm/
C, max.
APPLICATIONS
D
Caller Identification Delivery
D
FSK Demodulation
D
Data Synchronization
D
Tone Decoding
D
FM Detection
D
Carrier Detection
GENERAL DESCRIPTION
The XR-2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications
applications. It is particularly suited for FSK modem
applications. It operates over a wide supply voltage range
of 4.5 to 20V and a wide frequency range of 0.01Hz to
300kHz. It can accommodate analog signals between
10mV and 3V, and can interface with conventional DTL,
TTL, and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal within the pass band, a
quadrature phase detector which provides carrier
detection, and an FSK voltage comparator which provides
FSK demodulation. External components are used to
independently set center frequency, bandwidth, and output
delay. An internal voltage reference proportional to the
power supply is provided at an output pin.
The XR-2211 is available in 14 pin packages specified for
military and industrial temperature ranges.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XR-2211M
14 Pin CDIP (0.300")
-55
C to +125
C
XR-2211N
14 Pin CDIP (0.300")
-40
C to +85
C
XR-2211P
14 Pin PDIP (0.300")
-40
C to +85
C
XR-2211ID
14 Lead SOIC (Jedec, 0.150")
-40
C to +85
C
XR-2211
2
Rev. 3.01
INP
TIM C1
TIM C2
TIM R
V
REF
COMP I
9
NC
1
V
CC
4
GND
2
3
LDF
11
LDO
6
LDOQ
5
LDOQN
14
13
12
10
8
7
DO
Pre Amplifier
Lock
Detect
Comparator
Loop
q
-Det
Internal
Reference
V
REF
FSK Comp
Quad
q
-Det
VCO
Figure 1. XR-2211 Block Diagram
BLOCK DIAGRAM
XR-2211
3
Rev. 3.01
PIN CONFIGURATION
V
CC
14 Lead CDIP, PDIP (0.300")
TIM C1
TIM C2
TIM R
LDO
V
REF
NC
COMP I
INP
LDF
GND
LDOQN
LDOQ
DO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14 Lead SOIC (Jedec, 0.150")
14
1
2
3
4
5
6
7
13
12
11
10
9
8
V
CC
INP
LDF
GND
LDOQN
LDOQ
DO
TIM C1
TIM C2
TIM R
LDO
V
REF
NC
COMP I
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
V
CC
Positive Power Supply.
2
INP
I
Receive Analog Input.
3
LDF
O
Lock Detect Filter.
4
GND
Ground Pin.
5
LDOQN
O
Lock Detect Output Not. This output will be low if the VCO is in the capture range.
6
LDOQ
O
Lock Detect Output. This output will be high if the VCO is in the capture range.
7
DO
O
Data Output. Decoded FSK output.
8
COMP I
I
FSK Comparator Input.
9
NC
Not Connected.
10
V
REF
O
Internal Voltage Reference. The value of V
REF
is V
CC
/2 - 650mV.
11
LDO
O
Loop Detect Output. This output provides the result of the quadrature phase detection.
12
TIM R
I
Timing Resistor Input. This pin connects to the timing resistor of the VCO.
13
TIM C2
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
14
TIM C1
I
Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
XR-2211
4
Rev. 3.01
ELECTRICAL CHARACTERISTICS
Test Conditions: V
CC
= 12V, T
A
= +25
C, R
O
= 30K
W
, C
O
= 0.033
m
F, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
General
Supply Voltage
4.5
20
V
Supply Current
4
7
mA
R
0
> 10K
W
. See
Figure 4.
Oscillator Section
Frequency Accuracy
+1
+3
%
Deviation from f
O
= 1/R
0
C
0
Frequency Stability
Temperature
+20
+50
ppm/
C
See
Figure 8.
Power Supply
0.05
0.5
%/V
V
CC
= 12 +1V. See
Figure 7.
0.2
%/V
V
CC
= + 5V. See
Figure 7.
Upper Frequency Limit
100
300
kHz
R
0
= 8.2K
W
, C
0
= 400pF
Lowest Practical Operating
Frequency
0.01
Hz
R
0
= 2M
W
, C
0
= 50
m
F
Timing Resistor, R
0
- See
Figure 5
Operating Range
5
2000
K
W
Recommended Range
5
K
W
See
Figure 7 and Figure 8.
Loop Phase Dectector Section
Peak Output Current
+150
+200
+300
m
A
Measured at Pin 11
Output Offset Current
1
m
A
Output Impedance
1
M
W
Maximum Swing
+4
+ 5
V
Referenced to Pin 10
Quadrature Phase Detector
Measured at Pin 3
Peak Output Current
100
300
m
A
Output Impedance
1
M
W
Maximum Swing
11
V
PP
Input Preampt Section
Measured at Pin 2
Input Impedance
20
K
W
Input Signal
Voltage Required to
Cause Limiting
2
10
mV rms
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
XR-2211
5
Rev. 3.01
DC ELECTRICAL CHARACTERISTICS
(CONT'D)
Test Conditions:
V
CC
= 12V, T
A
= +25
C, R
O
= 30K
W
, C
O
= 0.033
m
F, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
Voltage Comparator Section
Input Impedance
2
M
W
Measured at Pins 3 and 8
Input Bias Current
100
nA
Voltage Gain
55
70
dB
R
L
= 5.1K
W
Output Voltage Low
300
500
mV
I
C
= 3mA
Output Leakage Current
0.01
10
m
A
V
O
= 20V
Internal Reference
Voltage Level
4.9
5.3
5.7
V
Measured at Pin 10
Output Impedance
100
W
AC Small Signal
Maximum Source Current
80
m
A
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply
20V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Signal Level
3V rms
. . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation
900mW
. . . . . . . . . . . . . . . . . . . . . . .
Package Power Dissipation Ratings
CDIP
750mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Above T
A
= 25
C
8mW/
C
. . . . . . . . . . . . . . .
PDIP
800mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Above T
A
= 25
C
60mW/
C
. . . . . . . . . . . . . .
SOIC
390mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Above T
A
= 25
C
5mW/
C
. . . . . . . . . . . . . . .
SYSTEM DESCRIPTION
The main PLL within the XR-2211 is constructed from an
input preamplifier, analog multiplier used as a phase
detector and a precision voltage controlled oscillator
(VCO). The preamplifier is used as a limiter such that
input signals above typically 10mV rms are amplified to a
constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
(unfiltered) produces sum and difference frequencies of
the input and the VCO output. The VCO is actually a
current controlled oscillator with its normal input current
(f
O
) set by a resistor (R
0
) to ground and its driving current
with a resistor (R
1
) from the phase detector.
The output of the phase detector produces sum and
difference of the input and the VCO frequencies
(internally connected). When in lock, these frequencies
are f
IN
+ f
VCO
(2 times f
IN
when in lock) and f
IN
- f
VCO
(0Hz
when lock). By adding a capacitor to the phase detector
output, the 2 times f
IN
component is reduced, leaving a
DC voltage that represents the phase difference between
the two frequencies. This closes the loop and allows the
VCO to track the input frequency.
The FSK comparator is used to determine if the VCO is
driven above or below the center frequency (FSK
comparator). This will produce both active high and
active low outputs to indicate when the main PLL is in lock
(quadrature phase detector and lock detector
comparator).
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