EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
(510) 668-7000
FAX (510) 668-7017
XR88C92/192
PLCC Package
DESCRIPTION
The XR88C92/192 is a Dual Universal Asynchronous Receiver and Transmitter with 8 (XR88C92) / 16 (XR88C192)
bytes transmit and receive FIFO. The XR88C92/192 is a pin and functional replacement for the SC26C92 and an
improved version of the Philips SCC2692 UART with faster data access and other additional features. The operating
speed of the receiver and transmitter can be selected independently from a table of eighteen fixed baud rates, a
16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external clock input. The XR88C92/192 provides a power-
down mode in which the oscillator is stopped but the register contents are retained. The XR88C92/192 is fabricated
in an advanced CMOS process to achieve low power and high speed requirements.
FEATURES
Added features in devices with top marking of "D2" and
newer:
5 volt tolerant inputs
Pin to pin and functional compatible to SC26C92
Enhanced Multidrop mode operation with separate
storage for address and data tags (9th bit)
8 Bytes transmit/receive FIFO (XR88C92)
16 Bytes transmit/receive FIFO (XR88C192)
Standard baud rates from 50bps to 230.4kbps
Non-standard baud rate of up to 1Mbps
Transmit and Receive trigger levels
Watch dog timer
Programmable clock source for receiver and trans-
mitter of each channel
Single interrupt output
7 Multipurpose inputs, 8 Multipurpose outputs
2.97 to 5.5 volt operation
Programmable character lengths (5, 6, 7, 8)
Parity, framing, and over run error detection
Programmable 16-bit timer/counter
On-chip crystal oscillator
Power down mode
DUAL UNIVERSAL ASYNCHRONOUS
RECEIVER AND TRANSMITTER
June 2003
6
5
4
3
2
1
44
43
42
41
40
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
18
19
20
21
22
23
24
25
26
27
28
A 3
IP 0
-IO W
-IO R
R X B
N .C .
T X B
O P 1
O P 3
O P 5
O P 7
-C S
R E S E T
X T A L 2
X T A L 1
R X A
N .C .
T X A
O P 0
O P 2
O P 4
O P 6
D1
D3
D5
D7
GN
D
N.
C
.
-IN
T
D6
D4
D2
D0
A2
IP1
A1
IP3
A0
N.
C
.
VC
C
IP4
IP5
IP6
IP2
X R 8 8 C 9 2
X R 8 8 C 1 9 2
Rev. 1.31
ORDERING INFORMATION
Part number
Package
Operating temperature Device Status
XR88C92CP
40-Lead PDIP
0 C
to
+ 70 C
Discontinued. See the XR88C92CV for a replacement.
XR88C92CJ
44-Lead PLCC
0 C
to
+ 70 C
Active
XR88C92CV
44-Lead TQFP
0 C
to
+ 70 C
Active
XR88C92IP
40-Lead PDIP
-40 C
to
+ 85 C
Discontinued. See the XR88C92IV for a replacement.
XR88C92IJ
44-Lead PLCC
-40 C
to
+ 85 C
Active
XR88C92IV
44-Lead TQFP
-40 C
to
+ 85 C
Active
XR88C192CP 40-Lead PDIP
0 C
to
+ 70 C
Discontinued. See the XR88C192CV for a replacement.
XR88C192CJ 44-Lead PLCC
0 C
to
+ 70 C
Active
XR88C192CV 44-Lead TQFP
0 C
to
+ 70 C
Active
XR88C192IP
40-Lead PDIP
-40 C
to
+ 85 C
Discontinued. See the XR88C192IV for a replacement.
XR88C192IJ
44-Lead PLCC
-40 C
to
+ 85 C
Active
XR88C192IV
44-Lead TQFP
-40 C
to
+ 85 C
Active
XR88C92/192
2
Rev. 1.31
40 Pin DIP Package
Package Description
44 Pin TQFP Package
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
A 0
IP 3
A 1
IP 1
A 2
A 3
IP 0
-IO W
-IO R
R X B
T X B
O P 1
O P 3
O P 5
O P 7
D 1
D 3
D 5
D 7
G N D
V C C
IP 4
IP 5
IP 6
IP 2
-C S
R E S E T
X T A L 2
X T A L 1
R X A
T X A
O P 0
O P 2
O P 4
O P 6
D 0
D 2
D 4
D 6
-IN T
XR
88C
9
2
XR
88C
1
9
2
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
1 0
1 1
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
12
13
14
15
16
17
18
19
20
21
22
A 3
IP 0
-IO W
-IO R
R X B
T X B
O P 1
O P 3
O P 5
O P 7
N .C .
-C S
R E S E T
X T A L 2
X T A L 1
R X A
T X A
O P 0
O P 2
O P 4
O P 6
N .C .
A2
IP
1
A1
IP
3
A0
VC
C
VC
C
IP
4
IP
5
IP
6
IP
2
D1
D3
D5
D7
GN
D
GN
D
-I
N
T
D6
D4
D2
D0
X R 88 C 92
X R 88 C 19 2
XR88C92/192
3
Rev. 1.31
Block Diagram
D 0 -D 7
-IO R
-IO W
R E S E T
A 0 -A 3
-C S
-IN T
X T A L 1
X T A L 2
In
t
e
rcon
n
e
c
t
B
u
s
L
i
n
e
s
&
C
o
nt
r
o
l
Si
g
n
al
s
C
l
ock &
Ba
u
d
R
a
t
e
Ge
n
e
r
a
t
o
r
In
t
e
rru
pt
Co
n
t
r
o
l
Lo
gi
c
Re
g
i
s
t
e
r
Se
l
e
c
t
Lo
gi
c
Da
t
a
Bu
s
Bu
f
f
e
r
s
&
C
o
nt
r
o
l
Lo
g
i
c
C h a n n el B
T X B
R X B
F lo w
C o n tr o l
L o g ic
T r a n s m it
S h ift
R e g is te r
T r a n s m it
F I F O
R e g is te r s
R e c e iv e
F I F O
R e g is te r s
F lo w
C o n tr o l
L o g ic
R e c e iv e
S h ift
R e g is te r
W a tc h
D o g
T im e r
T X A
R X A
C h a n n el A
F lo w
C o n tr o l
L o g ic
T r a n s m it
S h ift
R e g is te r
T r a n s m it
F I F O
R e g is te r s
R e c e iv e
F I F O
R e g is te r s
F lo w
C o n tr o l
L o g ic
R e c e iv e
S h ift
R e g is te r
W a tc h
D o g
T im e r
O P 0 -O P 7
IP 0 -IP 6
M u lti-
P u rp o se
I/O
C o n tro l
L o g ic
XR88C92/192
4
Rev. 1.31
SYMBOL DESCRIPTION (* 44 pin TQFP)
RXA, RXB
35,11
31,10
29,5
I
Serial data input. The serial information (data) received from
serial port to XR88C92/192 receive input circuit. A mark (high)
is logic one and a space (low) is logic zero.This input must
be held at logic one when idle and during power down.
TXA, TXB
33,13
30,11
28,6
O
Serial data output. The serial data is transmitted via this pin
with additional start , stop and parity bits. This output will be
held in mark (high) state during reset, local loop back mode
or when the transmitter is disabled.
RESET
38
34
32
I
Master Reset (active high). A high on this pin will reset all the
outputs and internal registers. The transmitter output and
the receiver input will be disabled during reset time.
OP0
32
29
27
O
Multi-purpose output. General purpose output or Channel A
Request-To-Send (-RTSA active low).
OP1
14
12
7
O
Multi-purpose output. General purpose output or Channel B
Request-To-Send (-RTSB active low).
OP2
31
28
26
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bits 1,0;
TxAClk1 -Transmit 1X clock.
TxAClk16 -Transmit 16X clock
RxAClk1 -Receive 1X clock
OP3
15
13
8
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bits 3,2;
C/T -Counter timer output (Open drain output)
TxBClk1 -Transmit 1X clock
RxBClk1 -Receive 1X clock
OP4
30
27
25
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bit 4;
-RxARDY -Receive ready signal (Open drain output)
-RxAFULL - Receive FIFO full signal (Open drain output)
Symbol
Pin
Signal
Pin Description
44
40
44*
type
XR88C92/192
5
Rev. 1.31
SYMBOL DESCRIPTION (* 44 pin TQFP)
OP5
16
14
9
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bit 5;
-RxBRDY - Receive ready signal (Open drain output)
-RxBFULL - Receive FIFO full signal (Open drain output)
OP6
29
26
24
O
Multi-purpose output. General purpose output or Transmit A
holding register empty interrupt (-TxARDY Open drain out-
put).
OP7
17
15
10
O
Multi-purpose output. General purpose output or Transmit B
holding register empty interrupt (-TxBRDY Open drain output)
A0-A3
2,4,
1,3,
40,42,
6,7
5,6
44,1
I
Address select lines. To select internal registers.
XTAL1
36
32
30
I
Crystal input 1 or external clock input. A crystal can be
connected between this pin and XTAL2 pin to utilize the
internal oscillator circuit. An external clock can be used to
clock internal circuit and baud rate generator for custom
transmission rates.
XTAL2
37
33
31
O
Crystal input 2 or buffered clock output. See XTAL1.
GND
22
20
16,17
Pwr
Signal and power ground.
-INT
24
21
18
O
Interrupt output (open drain, active low) This pin goes low
upon occurrence of one or more of eight maskable interrupt
conditions (when enabled by the interrupt mask register).
CPU can read the interrupt status register to determine the
interrupting condition(s). This output requires a pull-up resis-
tor.
IP0
8
7
2
I
Multi-purpose input or Channel A Clear-To-Send (-CTSA
active low).
IP1
5
4
43
I
Multi-purpose input or Channel B Clear-To-Send (-CTSB
active low).
IP2
40
36
34
I
Multi-purpose input or Timer/Counter External clock input.
Symbol
Pin
Signal
Pin Description
44
40
44*
type
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