XRD5408/10/12
5V, Low Power, Voltage Output
Serial 8/10/12-Bit DAC Family
Rev. 1.20
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017
E
2000
May 2000-2
FEATURES
D
8/10/12-Bit Resolution
D
Operates from a Single 5V Supply
D
Buffered Voltage Output: 13ms Typical Settling Time
D
240mW Total Power Consumption (typ)
D
Guaranteed Monotonic Over Temperature
D
Flexible Output Range: 0V to V
DD
D
8 Lead SOIC and PDIP Package
D
Power On Reset
D
Serial Data Output for Daisy Chaining
APPLICATIONS
D
Digital Calibration
D
Battery Operated Instruments
D
Remote Industrial Devices
D
Cellular Telephones
D
Motion Control
GENERAL DESCRIPTION
The XRD5408/10/12 are low power, voltage output
digital-to-analog converters (DAC) for +3V power supply
operation. The parts draw only 70mA of quiescent current
and are available in both an 8-lead PDIP and SOIC
package.
The XRD5408/10/12 have a 3 wire serial port with an
output allowing the user to daisy chain several of them
together. The serial port will support both Microwiret,
SPIt, and QSPIt standards.
The outputs of the XRD5408/10/12 are set at a gain of +2.
The output short circuit current is 7mA typical.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XRD5408AID
8 Lead 150 Mil JEDEC SOIC
-40C to +85C
XRD5408AIP
8 Lead 300 Mil PDIP
-40C to +85C
XRD5410AID
8 Lead 150 Mil JEDEC SOIC
-40C to +85C
XRD5410AIP
8 Lead 300 Mil PDIP
-40C to +85C
XRD5412AID
8 Lead 150 Mil JEDEC SOIC
-40C to +85C
XRD5412AIP
8 Lead 300 Mil PDIP
-40C to +85C
XRD5408/10/12
2
Rev. 1.20
BLOCK DIAGRAM
Figure 1. Block Diagram
Shift Register
-
+
V
REFIN
V
DD
CS
SCLK
SDIN
Power On
Reset
Switch
Matrix
AGND
V
DD
DOUT
V
OUT
R
R
2
n
PIN CONFIGURATION
V
DD
V
OUT
V
REFIN
AGND
SDIN
SCLK
CS
DOUT
8 Lead SOIC (Jedec, 0.150")
8
1
5
4
2
3
7
6
8 Lead PDIP (0.300")
V
DD
V
OUT
V
REFIN
AGND
SDIN
SCLK
CS
DOUT
1
2
3
4
8
7
6
5
PIN DESCRIPTION
Pin #
Symbol
Description
1
SDIN
Serial Data Input
2
SCLK
Serial Data Clock
3
CS
Chip Select (Active High)
4
DOUT
Serial Data Output
5
AGND
Analog Ground
6
V
REFIN
Voltage Reference Input
7
V
OUT
DAC Output
8
V
DD
Supply Voltage
XRD5408/10/12
3
Rev. 1.20
ELECTRICAL CHARACTERISTICS
Test Conditions: V
DD
= 5V, GND= 0V, REFIN= 2.048V (External), R
L
= 10kW, C
L
= 100pF, T
A
= T
MIN
to T
MAX
,
Unless Otherwise Noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Static Performance XRD5408
N
Resolution
8
Bits
INL
Relative Accuracy
0.25
0.5
LSB
DNL
Differential Nonlinearity
0.25
0.5
LSB
Guaranteed Monotonic
V
OS
Offset Error
0
3
8
mV
TCV
OS
Offset Tempco
2
ppm/C
PSRR
Offset-Error Power-Supply
Rejection Ratio
0.5
1
mV
4.5V V
DD
5.5V
GE
Gain Error
0.1
0.4
%FS
TCGE
Gain-Error Tempco
10
ppm/C
PSRR
Power-Supply
Rejection Ratio
0.1
1.25
mV
4.5V V
DD
5.5V, Measured at
FS
Static Performance XRD5410
N
Resolution
10
Bits
INL
Relative Accuracy
0.5
1
LSB
DNL
Differential Nonlinearity
0.25
0.5
LSB
Guaranteed Monotonic
V
OS
Offset Error
0
3
8
mV
TCV
OS
Offset Tempco
2
ppm/C
PSRR
Offset-Error Power-Supply
Rejection Ratio
0.5
1
mV
4.5V V
DD
5.5V
GE
Gain Error
0.1
0.4
%FS
TCGE
Gain-Error Tempco
10
ppm/C
PSRR
Power-Supply
Rejection Ratio
0.1
1.25
mV
4.5V V
DD
5.5V, Measured at
FS
Static Performance XRD5412
N
Resolution
12
Bits
INL
Relative Accuracy
2
4
LSB
DNL
Differential Nonlinearity
0.5
-1
LSB
Guaranteed Monotonic
+1.25
LSB
V
OS
Offset Error
0
3
8
mV
TCV
OS
Offset Tempco
2
ppm/C
PSRR
Offset-Error Power-Supply
Rejection Ratio
0.5
1
mV
4.5V V
DD
5.5V
GE
Gain Error
0.1
0.4
%FS
TCGE
Gain-Error Tempco
10
ppm/C
PSRR
Power-Supply
Rejection Ratio
0.1
1.25
mV
4.5V V
DD
5.5V, Measured at
FS
XRD5408/10/12
4
Rev. 1.20
ELECTRICAL CHARACTERISTICS
(CONT'D)
Test Conditions: V
DD
= 5V, GND= 0V, REFIN= 2.048V (External), R
L
= 10kW, C
L
= 100pF, T
A
= T
MIN
to T
MAX
,
Unless Otherwise Noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Voltage Output (V
OUT
) XRD5408/10/12
V
O
Output Voltage Range
0
V
DD
--0.4
V
V
REG
Output Load Regulation
2
4
mV
V
OUT
= 2V, R
L
=2kW
+I
SC
Short-Circuit Current, Sink
13
mA
V
OUT
= V
DD
-I
SC
Short-Circuit Current, Source
7
mA
V
OUT
= GND
Voltage Reference Input (V
REFIN
) XRD5408/10/12
V
REFIN
Voltage Range
0
V
DD
V
Output Swing Limited, Not Code Dependent
R
IN
Input Resistance
40
65
kW
TCR
IN
Input Resistance Tempco
1500
ppm/C
C
IN
Input Capacitance
32
40
pF
Not Code Dependent
AC
FT
AC Feedthrough
-80
dB
REFIN = 1kHz, 2Vp-p, SD
IN
=000h
Digital Inputs (SDIN, SCLK, CS) XRD5408/10/12
V
IH
Input High
3.5
V
V
IL
Input Low
1
V
I
IN
Input Current
1
mA
V
IN
=0V or V
DD
C
IN
Input Capacitance
10
pF
Digital Output (DOUT) XRD5408/10/12
V
OH
Output High
V
DD
-1
V
I
SOURCE
=4mA
V
OL
Output Low
0.4
V
I
SINK
=4mA
Dynamic Performance XRD5408/10/12
SR
Voltage-Output Slew Rate
0.13
0.21
V/ms
T
A
=+25C
t
s
Voltage-Output Settling Time
13
15
ms
1/2LSB, V
OUT
=2V
D
FT
Digital Feedthrough
1
nV-s
CS=V
DD
, SDIN=SCLK=100kHz
SINAD
Signal-to-Noise Plus Distortion
68
dB
V
REFIN
=1kHz, 2Vp-p F.S., SDIN=Full
Scale, --3dB BW=250kHz
Power Supply XRD5408/10/12
V
DD
Positive Supply Voltage
4.5
5.5
V
I
DD
Power Supply Current
35
60
mA
All Inputs=0V or V
DD
, Output=No Load,
I
REF
Not Included, V
O
=0V (Note
1
)
Switching Characteristics XRD5408/10/12
t
CSS
CS Setup Time
10
20
ns
t
CSH0
SCLK Fall to CS Fall Hold Time
5
ns
t
CSH1
SCLK Fall to CS Rise Hold TIme
0
ns
t
CH
SCLK High Width
20
35
ns
t
CL
SCLK Low Width
20
35
ns
Notes:
1
Total supply current consumption = I
DD
+ I
REF
+ (V
O
/ 70K.)
XRD5408/10/12
5
Rev. 1.20
ELECTRICAL CHARACTERISTICS
(CONT'D)
Test Conditions: V
DD
= 5V, GND= 0V, REFIN= 2.048V (External), R
L
= 10kW, C
L
= 100pF, T
A
= T
MIN
to T
MAX
,
Unless Otherwise Noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
t
DS
D
IN
Setup Time
10
45
ns
t
DH
D
IN
Hold Time
0
ns
t
DO
D
OUT
Valid Propagation Delay
8
15
ns
C
L
= 50pF
t
CSW
CS High Pulse Width
20
40
ns
t
CS1
CS Rise to SCLK Rise Setup
Time
10
20
ns
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND
-0.3V, +7V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Input Voltage to GND
-0.3V, V
DD
+0.3V
. . . . . .
V
REFIN
-0.3V, V
DD
+0.3V
. . . . . . . . . . . . . . . . . . . . . . . . .
V
OUT
1
V
DD
, GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Current, Any Pin
-20mA, +20mA
. . . . . . . .
Package Power Dissipation Ratings (T
A
= +70C)
PDIP (derate 9mW/C above +70C)
117mW
. . . .
SOIC (derate 6mW/C above +70C)
155mW
. . .
Operating Temperature Range
-40C to + 85C
. . . . .
Storage Temperature Range
-65C to +165C
. . . . . .
Lead Temperature (soldering, 10 sec)
+300C
. . . . . .
Notes
1
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100
m
s.
XRD5408/10/12
6
Rev. 1.20
TIMING
CS
SCLK
SDIN
DOUT
t
CSW
t
CS1
t
CSH1
t
CL
t
D0
t
DH
t
DS
t
CH
t
CSS
t
CSH0
Figure 2. Timing Diagram
Input
Output
1111
1111
(0000)
1000
0001
(0000)
1000
0000
(0000)
0111
1111
(0000)
0000
0001
(0000)
0000
0000
(0000)
0V
Note:
Write 8-bit data words with four sub-LSB 0s because the DAC input latch
is 12 bits wide.
Table 1. Binary Code Table
+ 2 (V
REFIN
) 127
256
+ 2 (V
REFIN
) 129
256
+ 2 (V
REFIN
) 255
256
+ 2 (V
REFIN
) 128
256 = +
V
REFIN
+ 2 (V
REFIN
) 1
256
XRD5408/10/12
7
Rev. 1.20
THEORY OF OPERATION
XRD5408/10/12 Description
The XRD5408/10/12 are micro-power, voltage output,
serial daisy-chain programmable DACs operating from a
single 5V power supply. The DACs are built on a 0.6
micron CMOS process. The features of these DACs
make it well suited for industrial control, low distortion
audio, battery operated devices and cost sensitive
designs that want to minimize pin count on ICs.
Resistor String DAC
A resistor string architecture converts digital data using a
switch matrix to an analog signal as shown in
Figure 3.
Figure 3. XRD5408/10/12 DAC Architecture
Shift Register
-
+
V
REFIN
V
DD
CS
SCLK
SDIN
Power On
Reset
Switch
Matrix
AGND
V
DD
DOUT
V
OUT
R
R
2
n
The resistor string architecture provides a non-inverted
output voltage (V
OUT
) of the reference input (V
REFIN
) for
single supply operation while maintaining a constant input
resistance.
Unlike inverted R-2R architectures the
reference input resistance will remain constant
independent of code. This greatly simplifies the analog
driving source requirements for the reference voltage and
minimizes distortion. Similarly input capacitance varies
only approximately 4pF over all codes.
Fixed Gain +2 Voltage Output Amplifier
A high open-loop gain operational amplifier buffers the
resistor string with a stable, fixed gain of +2. The voltage
output will settle within 13 s. The output is short circuit
protected and can regulate an output load of 2V into 2k
within 2mV at 25C.
While the reference input will accept a voltage from
rail-to-rail, the linear input voltage range is constrained by
the output swing of the fixed +2 closed-loop gain amplifier.
Full scale output swing is achieved with an external
reference of approximately 1/2 V
DD
. The reference
voltage must be positive because the XRD5408/10/12
DAC is non-inverting.
Serial Daisy-Chainable Digital Interface
The three wire serial interface includes a DOUT to enable
daisy-chaining of several DACs. This minimizes pin
count necessary of digital asics or controllers to address
multiple DACS. The serial interface is designed for
CMOS logic levels. Timing is shown in
Figure 2. The
binary coding table (
Table 1) shows the DAC transfer
function.
A power on reset circuit forces the DAC to reset to all "0"s
on power up.
APPLICATION NOTES
Serial Interface
The XRD5408/10/12 family has a three wire serial
interface that is compatible with Microwiret, SPIt and
QSPIt standards. Typical configurations are shown in
Figure 4 and Figure 5. Maximum serial port clock rate is
limited by the minimum pulse width of t
CH
and t
CL
.
Feedthrough noise from the serial port to the analog
output (V
OUT
) is minimized by lowering the frequency of
the serial port and holding the digital edges to >5ns.
XRD5408/10/12
8
Rev. 1.20
Microwire
t
Port
SK
SO
I/O
SCLK
SDIN
CS
V
OUT
GND
V
DD
V
REFIN
XRD5412
1.25V
MP5010
+5V
0-2.5V
+5V
0.1mF
Figure 4. Typical Microwiret Application Circuit
SPI
t
Port
SK
MOSI
I/O
SCLK
SDIN
CS
V
OUT
GND
V
DD
V
REFIN
XRD5410
1.25V
MP5010
+5V
0-2.5V
+5V
0.1mF
Figure 5. Typical SPIt Application Circuit
XRD5408/10/12
9
Rev. 1.20
Figure 6. Shift Register Format
DOUT
SDIN
X
X
X
X
DAC
MSB
n
The DACs are programmed by a 16 bit word of serial data.
The format of the serial input register is shown in Figure 6.
The leading 4 bits are not used to update the DAC. If the
DAC is not daisy-chained then only a 12 bit serial word is
needed to program the DAC. The next 8, 10 or 12 bits
after the 4 leading bits are data bits. The XRD5408's first
8 bits are valid data and the trailing 4 bits must be set to 0.
Figure 7 demonstrates the 16 bit digital word for the 8,
10,12 bit DACs.
Part
Leading
Unused
Bits
Data Bits
MSB
LSB
Trailing
"0"
Bits
XRD5412
XXXX
XXXXXXXX
None
XRD5410
XXXX
XXXXXXXX
00
XRD5408
XXXX
XXXXXXXX
0000
Table 2. 16-Bit Digital Word Register for XRD5408,
XRD5410, XRD5412.
SCLK should be held low when CS transitions low. Data is
clocked in on the rising edge of SCLK when CS is low.
SDIN data is held in a 16 bit serial shift register. The DAC
is updated with the data bits on the rising edge of CS.
When CS is high data is not shifted into the
XRD5408/10/12.
Daisy-Chaining
The digital output port (DOUT) has a 4mA drive for greater
fan-out capability when daisy-chaining. DOUT allows
cascading of multiple DACs with the same serial data
stream. The data at SDIN appears at DOUT after 16 clock
cycles plus one clock width (t
CH
) and a propagation delay
(t
DO
). DOUT remains in the state of the last data bit when
CS is high. DOUT changes on the falling edge of SCLK
when CS is low.
Any number of DACs can be connected in this way by
connecting DOUT of one DAC to SDIN of the next DAC.
AC
FT
Feedthrough (DAC Code = 0)
AC Feedthrough from V
REFIN
to V
OUT
is minimized with
low impedance grounding as shown in
Figure 7. If the
DAC data is set to all "0"s then V
OUT
is a function of the
divider between the DAC string impedance and ground
impedance. See the Power Supply and Grounding
section for recommendations.
The typical AC
feedthrough for a 1kHz 2Vpp signal with code = 0 is
-80dB.
Figure 7. AC
FT
Feedthrough Equivalent
Circuit, DAC Code =0
V
REFIN
XRD5408/10/12
V
OUT
GND
RGND
Analog GND
R
IN
--
+
Compatible with MAX515 & MAX539
The XRD5408/10/12 family of DACs are functionally
campatible with the MAX515 & MAX539 while providing
significant improvements. The XRD5408/10/12 DACs
have lower power, faster serial ports, and a constant
reference impedance to minimize the reference driving
requirements and maximize system linearity. The DOUT
XRD5408/10/12
10
Rev. 1.20
port also has 4mA driving capability for greater fan-out
when daisy-chaning to other digital inputs.
Monotonicity
The XRD5408/10/12 family of DACs are monotonic over
the entire temperature range.
Micro-Power Operation
The XRD5408 is the lowest power in their class. The
quiescent current rating does not include the reference
ladder current. Power can be saved when the part is not in
use by setting the DAC code to all "0"s assuming the
output load is referenced to ground. This minimizes the
DAC output load current. An analog switch placed in
series with the reference ladder can toggle the reference
voltage off when the circuit is inactive to minimize power
consumption.
Power Supply and Grounding
Best parametric results are obtained by powering the
XRD5408/10/12 family of DACs from an analog +5V
power supply and analog ground. Digital power supplies
and grounds should be separated or connected to the
analog supplies and grounds only at the low-impedance
power-supply source. This is best accomplished on a
multilayer PCB with dedicated planes to ground and
power. The DACs should be locally bypassed with both
0.1 F and 2.2 F capacitors mounted as close as possible
to the power supply pin (V
DD
). Surface mount ceramic
capacitors are recommended for low impedance, wide
band power supply bypass. If only one +5V power supply
is available for both analog and digital circuity isolate the
analog power supply to the XRD5408/10/12 DAC with an
inductor or ferrite bead before the local bypass
capacitors.
PERFORMANCE CHARACTERISTICS
Figure 8. XRD5408 INL
Figure 9. XRD5408 DNL
L
S
B
CODE
L
S
B
CODE
--0.2
0
0.2
0.4
0
64
128
192
--0.1
0.0
0.2
0.35
255
0
64
128
192
255
XRD5408/10/12
11
Rev. 1.20
Figure 10. Output Source Current
vs. Output Voltage
0
5
0.5V/div
10
1mA/div
0
0
1
0.1V/div
Figure 11. Output Sink Current
vs. Output Voltage
Figure 12. Output Sink and Source Cur-
rent vs. Output Volatge
0
1.5mA/div
--15
5
0
0.1V/div
7
0
2mA/div
--14
I O
(
m
A
)
V
OUT
(V)
I O
(
m
A
)
I O
(
m
A
)
V
OUT
(V)
V
OUT
(V)
XRD5408/10/12
12
Rev. 1.20
V
OUT
CS
Figure 13. Voltage Output Settling Time (t
s
),
V
DD
= 5V, V
REFIN
= 1V, No Load
20
22
24
26
28
30
32
34
36
38
40
-40
-20
0
20
40
60
80
100
Temp (C)
Figure 14. I
DD
vs. Temperature
I
D
D
A
)
(
XRD5408/10/12
13
Rev. 1.20
Figure 15. Closed Loop Gain vs. Frequency
-2
-1
0
1
2
3
4
5
6
7
8
10
100
1000
Frequency (KHz)
G
a
i
n
(
d
B
)
Figure 16. Closed Loop Phase vs. Frequency
-120
-100
-80
-60
-40
-20
0
10
100
1000
Frequency (KHz)
P
h
a
s
e
(
)
Microwiret
is a trademark of National Semiconductor Corproation.
SPIt
and QSPIt are trademarks of Motorola Corporation.
XRD5408/10/12
14
Rev. 1.20
SYMBOL
MIN
MAX
MIN
MAX
A
0.053
0.069
1.35
1.75
A
1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.189
0.197
4.80
5.00
E
0.150
0.157
3.80
4.00
e
0.050 BSC
1.27 BSC
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
a
0
8
0
8
INCHES
MILLIMETERS
8 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
e
8
5
4
D
E
H
B
A
L
C
A
1
Seating
Plane
a
Note: The control dimension is the millimeter column
XRD5408/10/12
15
Rev. 1.20
8 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 2.00
8
1
5
4
D
A
1
E
1
E
A
L
Seating
Plane
SYMBOL
MIN
MAX
MIN
MAX
INCHES
A
0.145
0.210
3.68
5.33
A
1
0.015
0.070
0.38
1.78
A
2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B
1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
0.348
0.430
8.84
10.92
E
0.300
0.325
7.62
8.26
E
1
0.240
0.280
6.10
7.11
e
0.100 BSC
2.54 BSC
e
A
0.300 BSC
7.62 BSC
e
B
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
4.06
a
0
15
0
15
MILLIMETERS
A
2
a
e
B
C
e
B
1
B
Note: The control dimension is the inch column
e
A
XRD5408/10/12
16
Rev. 1.20
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
All trademarks and registered trademarks are property of their respective owners.
Copyright 2000 EXAR Corporation
Datasheet May 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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