EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
(510) 668-7000
FAX (510) 668-7017
Rev. 3.00
XRD8785
CMOS 8-Bit High Speed
Analog-to-Digital Converter
April 2002
FEATURES
8-Bit Resolution
Up to 20 MHz Sampling Rate
Internal S/H Function
Single Supply: 5V
VIN DC Range: 0V to V
DD
VREF DC Range: 1V to V
DD
Low Power: 75mW typ. (excluding reference)
Latch-Up Free
ESD Protection: 2000V Minimum
GENERAL DESCRIPTION
The XRD8785 is an 8-bit Analog-to-Digital Converter.
Designed using an advanced 5V CMOS process, this
part offers excellent performance, low power con-
sumption, and latch-up free operation.
This device uses a two-step flash architecture to
maintain low power consumption at high conversion
rates. The input circuitry of the XRD8785 includes an
on-chip S/H function which allows the user to digitize
analog input signals between AGND and AV
DD
. Careful
design and chip layout have achieved a low analog
input capacitance. This reduces "kickback" and eases
the requirements of the buffer/amplifier used to drive
the XRD8785. The designer can choose the internally
generated reference voltages by connecting V
RB
to
20-Pin Package Available: XRD8775
3V Version: XRD87L85
APPLICATIONS
Digital Color Copiers
Cellular Telephones
CCDs and Scanners
Video Capture Boards
V
RBS
and V
RT
to V
RTS
, or provide external reference
voltages to the V
RB
and V
RT
pins. The internal reference
generates 0.6V at V
RB
and 2.6 V at V
RT
. Providing
external reference voltages allows easy interface to
any input signal range between AGND and AV
DD
. This
also allows the system to adjust these voltages to
cancel zero scale and full scale errors, or to change the
input range as needed.
The device operates from a single +5V supply. Power
consumption is 75mW at FS = 15MHz. Specified for
operation over the commercial/industrial (40 to
+85C) temperature range, the XRD8785 is available in
Plastic Dual-in-line (PDIP), Surface Mount (SOIC) and
Small Outline (SOP) packages in EIAJ and JEDEC.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
XRD8785
2
Rev. 3.00
24-Pin PDIP (300 MIL) - P24
ORDERING INFORMATION
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
24-Pin SOP (EIAJ, 5.4mm) K24
24-Pin SOIC (Jedec, 300 MIL) D24
PIN OUT DEFINITIONS
PIN NO.
NAME
DESCRIPTION
1
OE
Output Enable
2
DGND
Digital Ground
3
DB0
Data Output Bit 0 (LSB)
4
DB1
Data Output Bit 1
5
DB2
Data Output Bit 2
6
DB3
Data Output Bit 3
7
DB4
Data Output Bit 4
8
DB5
Data Output Bit 5
9
DB6
Data Output Bit 6
10
DB7
Data Output Bit 7 (MSB)
11
DV
DD
Digital Power Supply
12
CLK
Sampling Clock Input
PIN NO.
NAME
DESCRIPTION
13
DV
DD
Digital Power Supply
14
AV
DD
Analog Power Supply
15
AV
DD
Analog Power Supply
16
V
RTS
Generates 2.6 V if tied to V
RT
17
V
RT
Top Reference
18
AV
DD
Analog Power Supply
19
VIN
Analog Input
20
AGND
Analog Ground
21
AGND
Analog Ground
22
V
RBS
Generates 0.6 V if tied to V
RB
23
V
RB
Bottom Reference
24
DGND
Digital Ground
Package
Temperature
Part No.
DNL
INL
Type
Range
(LSB)
(LSB)
SOIC (Jedec)
40 to +85C
XRD8785AID
+/- 0.75
+/-1.5
SOP (EIAJ)
40 to +85C
XRD8785AIK
+/- 0.75
+/-1.5
Plastic Dip (300MIL)
40 to +85C
XRD8785AIP
+/- 0.75
+/-1.5
XRD8785
3
Rev. 3.00
ELECTRICAL CHARACTERISTICS TABLE
UNLESS OTHERWISE SPECIFIED: AV
DD
= DV
DD
= 5V, FS = 15MHZ (50% DUTY CYCLE),
V
RT
= 2.6V, V
RB
= 0.6V, T
A
= 25C
25C
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions/Comments
KEY FEATURES
Resolution
8
Bits
Sampling Rate
FS
0.1
15
20
MHz
ACCURACY
Differential Non-Linearity
DNL
+/-0.75
LSB
@ 15MHz
Differential Non-Linearity
DNL
+/-0.5
LSB
@ 10MHz
Integral Non-Linearity
INL
+/-1.5
LSB
Best Fit Line
(Max INL Min INL)/2
Zero Scale Error
EZS
+3
LSB
Full Scale Error
EFS
-2
LSB
REFERENCE VOLTAGES
Positive Ref. Voltage
V
RT
2.6
AV
DD
V
Negative Ref. Voltage
V
RB
AGND
0.6
V
Differential Ref. Voltage
3
V
REF
1.0
AV
DD
V
V
REF
= V
RT
V
RB
Ladder Resistance
R
L
245
350
550
Ladder Temp. Coefficient
R
TCO
2000
ppm/C
Self Bias 1
Short V
RB
and V
RBS
V
RB
0.6
V
Short V
RT
and V
RTS
V
RT
-V
RB
2
V
Self Bias 2
V
RB
= AGND,
V
RT
2.3
V
Short V
RT
and V
RTS
ANALOG INPUT
Input Bandwidth (1 dB)
2, 4
BW
50
MHz
Input Voltage Range
V
IN
V
RB
V
RT
V
Input Capacitance
5
C
IN
16
pF
Aperture Delay
2
t
AP
3
ns
DIGITAL INPUTS
Logical "1" Voltage
V
IH
4.0
V
Logical "0" Voltage
V
IL
1.0
V
DC Leakage Currents
6
I
IN
V
IN
=DGND to DV
DD
CLK
5
A
OE
5
A
Input Capacitance
5
pF
Clock Timing ( See Figure 1.)
7
Clock Period
1/FS
50
66.7
ns
High Pulse Width
t
PWH
25
33.3
ns
Low Pulse Width
t
PWL
25
33.3
ns
DIGITAL OUTPUTS
C
OUT
=15 pF
Logical "1" Voltage
V
OH
4.5
V
I
LOAD
= 4 mA
Logical "0" Voltage
V
OL
0.4
V
I
LOAD
= 4 mA
3-state Leakage
I
OZ
10
A
V
OUT
=DGND to DV
DD
Data Valid Delay
8
t
DL
10
ns
Data Enable Delay
t
DEN
5
ns
Data 3-state Delay
t
DHZ
5
ns
XRD8785
4
Rev. 3.00
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
UNLESS OTHERWISE SPECIFIED: AV
DD
= DV
DD
= 5V, FS = 15MHZ (50% DUTY CYCLE),
V
RT
= 2.6V, V
RB
= 0.6V, T
A
= 25C
25C
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions/Comments
AC PARAMETERS
Differential Gain Error
dg
2
%
FS = 4 x NTSC
Differential Phase Error
d
ph
1
Degree
FS = 4 x NTSC
POWER SUPPLIES
Operating Voltage (AV
DD
, DV
DD
)
9
V
DD
4.5
5
5.5
V
Current (AGND + DGND)
I
DD
15
25
mA
Does not include ref. current
NOTES
1. The difference between the measured and the ideal code width (V
REF
/256) is the DNL error (Figure 3). The INL error is the maximum distance (in LSBs) from the best fit line to any transition
voltage (Figure 4). Accuracy is a function of the sampling rate (FS).
2. Guaranteed, not tested
3. Specified values guarantee functionality. Refer to other parameters for accuracy.
4. 1dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth.
5. See V
IN
input equivalent circuit (Figure 5). Switched capacitor analog input requires driver with low output resistance.
6. All inputs have diodes to DV
DD
and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DV
DD
.
7. t
R
, t
F
should be limited to >5ns for best results.
8. Depends on the RC load connected to the output pin.
9. AGND & DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (
T
A
= +25
C unless otherwise noted)
1, 2, 3
V
DD
to GND .......................................................... 7V
V
RT
& V RB ......................... V
DD
+0.5 to GND 0.5V
V
IN
..................................... V
DD
+0.5 to GND 0.5V
All Inputs ............................ V
DD
+0.5 to GND 0.5V
All Outputs ......................... V
DD
+0.5 to GND 0.5V
Storage Temperature .........................65 to +150C
Lead Temperature (Soldering 10 seconds) ... +300C
Package Power Dissipation Rating @ 75C
PDIP, SOIC, SOP ................................. 675mW
Derates above 75C ........................... 12mW/C
NOTES:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification
is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection
diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms.
3. V
DD
refers to AV
DD
and DV
DD
. GND refers to AGND and DGND.
XRD8785
5
Rev. 3.00
Figure 1. XRD8785 Timing Diagram
Figure 2. Output Enable/Disable Timing Diagram
Figure 3. DNL Measurement
Figure 4. INL Error Calculation
XRD8785
6
Rev. 3.00
Figure 5. Equivalent Input Circuit
Figure 6. Typical Circuit Connections
APPLICATION NOTES
Signals should not exceed V
DD
+0.5V or go below GND
0.5V. All pins have internal protection diodes that will
protect them from short transients (<100
s) outside
the supply range.
AGND and DGND pins are connected internally
through the P-substrate. DC voltage differences be-
tween GND pins will cause undesirable internal sub-
strate currents.
The power supply (V
DD
) and reference voltage (V
RT
&
V
RB
) pins should be decoupled with 0.1
F and 10
F
capacitors to AGND, placed as close to the chip as
possible.
The digital outputs should not drive long wires or buses.
The capacitive coupling and reflections will contribute
noise to the conversion.
To avoid timing errors, use the rising edge of the sample
clock (CLK) to latch data from the XRD8785 to other
parts of the system.
The reference can be biased internally by shorting V
RT
to V
RTS
and V
RB
to V
RBS
. This will generate 0.6V at V
RB
and 2.6V at V
RT
(see Figure 5).
If the internal reference pins V
RTS
and/or V
RBS
are not
used, they should be left unconnected.
The output enable pin (OE) should not be left uncon-
nected. If not controlled by an active signal then it must
be tied to a logic low value.
XRD8785
7
Rev. 3.00
PERFORMANCE CHARACTERISTICS
Graph 1. DNL vs. Code
Graph 2. INL vs. Code
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
32
64
96
128
160
192
224
256
Code
DNL (LSB)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Fs = 15MHz
Ta = 25
o
C
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
32
64
96
128
160
192
224
256
Code
INL (LSB)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Fs = 15MHz
Ta = 25
o
C
XRD8785
8
Rev. 3.00
Graph 3. DNL vs. Sampling Frequency
Graph 4. Best Fit INL vs. Sampling Frequency
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0.10
1.00
10.00
100.00
Fs (MHz)
DNL (LSB)
POS DNL
NEG DNL
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Ta = 25
o
C
0.0
0.2
0.4
0.6
0.8
1.0
0.10
1.00
10.00
100.00
Fs (MHz)
INL (LSB)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Ta = 25
o
C
XRD8785
9
Rev. 3.00
Graph 6. Supply Current vs. Temperature
Graph 5. IDD vs. Sampling Frequency
0
4
8
12
16
20
24
0
5
10
15
20
25
30
Fs (MHz)
Idd (mA)
Vdd = 5.5V
Vdd = 5.0V
Vdd = 4.5V
Ta = 25
o
C
0
2
4
6
8
10
12
14
16
18
20
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
Idd (mA)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Fs = 20MHz
Fs = 15MHz
Fs = 10MHz
XRD8785
10
Rev. 3.00
Graph 7. Ladder Resistance vs. Temperature
Graph 8. SNR vs. Input Frequency
250
300
350
400
450
500
550
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
Ladder Resistance (ohm)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
0
5
10
15
20
25
30
35
40
45
50
0.01
0.1
1
10
Fin (MHz)
SNR (dB)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Fs = 15MHz
Ta = 25
o
C
XRD8785
11
Rev. 3.00
Graph 9. SINAD vs. Input Frequency
Graph 10. FFT Plot
0
5
10
15
20
25
30
35
40
45
50
0.01
0.1
1
10
Fin (MHz)
SINAD (dB)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Fs = 15MHz
Ta = 25
o
C
-120
-100
-80
-60
-40
-20
0
20
40
60
80
0.0
1.5
3.0
4.5
6.0
7.5
Freq (MHz)
Amplitude (dB)
Vdd = 5.0V
Vrt = 2.6V
Vrb = 0.6V
Fs = 15MHz
Fin = 500KHz
XRD8785
12
Rev. 3.00
24
1
13
12
D
e
B
1
A
1
E
1
E
A
L
B
Seating
Plane
A
2
C
e
B
e
A
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.145
0.210
3.68
5.33
A1
0.015
0.070
0.38
1.78
A2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
1.125
1.275
28.58
32.39
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
0.100 BSC
2.54 BSC
eA
0.300 BSC
7.62 BSC
eB
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
5.08
a
0
15
0
15
Note: The control dimension is the inch column
24 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
REV. 1.00
XRD8785
13
Rev. 3.00
24 LEAD EIAJ SMALL OUTLINE
(5.4 mm EIAJ SOP)
REV. 1.00
e
D
E
H
B
A
1
Seating
Plane
24
13
12
A
2
1
A
L
C
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.069
0.083
1.75
2.10
A1
0.002
0.008
0.05
0.20
A2
0.067
0.075
1.70
1.90
B
0.012
0.020
0.30
0.50
C
0.004
0.008
0.10
0.20
D
0.587
0.594
14.90
15.10
E
0.209
0.217
5.30
5.50
e
0.050 BSC
1.27 BSC
H
0.299
0.315
7.60
8.00
L
0.012
0.030
0.30
0.76
a
0
10
0
10
XRD8785
14
Rev. 3.00
e
D
E
H
B
A
1
Seating
Plane
24
13
12
1
A
L
C
24 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
REV. 1.00
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.009
0.013
0.23
0.32
D
0.598
0.614
15.20
15.60
E
0.291
0.299
7.40
7.60
e
0.050 BSC
1.27 BSC
H
0.394
0.419
10.00
10.65
L
0.016
0.050
0.40
1.27
a
0
8
0
8
XRD8785
15
Rev. 3.00
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of
patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending
upon a user's specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright 2002 EXAR Corporation
Datasheet April 2002
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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