EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
(510) 668-7000
FAX (510) 668-7017
Rev. P1.10
Preliminary
XRD98L60
CCD Image Digitizer
CDS/PGA/ADC
June 1999-2
FEATURES
40 MSPS, 10-Bit Resolution
Low Power CMOS: 210mW, V
DD
= 3V
Reduced Power Mode for Slower Pixel Rates
Correlated Double Sample/Hold (CDS)
Programmable CDS Aperture Delays
Automatic Black Level Offset Compensation
Programmable Gain (10-Bit) 0dB to 32dB
Low Noise: SNR = 54 dB (at min. PGA gain)
Single 3V Power Supply (2.7V to 3.3V)
Standard Three Wire Serial Interface
Power Down Mode, Less Than 1mW
Two Serial Controlled, 8-Bit D/A Converters
ESD Protection to Over 2000V
48-Pin TQFP Package
APPLICATIONS
Video Camcorders
DVC
HDTV
Digital Still Cameras
GENERAL DESCRIPTION
The XRD98L60 is an analog-to-digital interface for CCD
based video and still cameras. This chip includes a
Correlated Double Sample/Hold (CDS), a Program-
mable Gain Amplifier (PGA), a low power 10 bit Ana-
log-to-Digital Converter (ADC), black level offset cali-
bration, and two serial controlled Digital-to-Analog
Converters (DACs). The PGA, offset calibration, DACs,
and other setup controls are programmed through a
simple three wire serial interface. The entire chip
operates from a single 3.0V supply (2.7V minimum).
With V
DD
=3.0V the chip draws 70mA. For maximum
power savings, the Power Down mode can be used to
drop the supply current below 300
A.
ORDERING INFORMATION
Part No.
Package Type
Temperature Range
XRD98L60AIV
48-Lead TQFP
-40C to +85C
XRD98L60
2
Rev. P1.10
Preliminary
Figure 1. Simplified Block Diagram of the XRD98L60
ADC
CDS
PGA
CCDin
REFin
SPIX
SBLK
CLAMP
CapP
CapN
Over
reg
Serial Port
Registers
Timing
Generator
GND
(outputs)
DVDD
VDD (3)
GND (3)
GND (2)
(substrate)
SCLK
SDI
LOAD
Offset
Calibration
PGAoutN
ADCinP
CAL
ADCLK
RESET
ExtRef
Power Down
8 bit
8 bit
DAC0
DAC1
Test1
Test2
Test
XRD98L60
10
OK
DB[9:0]
ADCinN
PGAoutP
XRD98L60
3
Rev. P1.10
Preliminary
PIN DESCRIPTION
Pin #
Name
Type (1)
Description
3-5, 8-11, 13-15
DB0-DB9
DO
ADC Digital Outputs. DB0 is the LSB. DB9 is the MSB.
16
OVER
DO
Over Range Output. OVER goes high to indicate the ADC input
voltage is outside the ADC reference range (too high or too low).
When OVER goes high, DB[9:0] will output full-scale code (all 1's) if
the input is too high, or zero scale code (all 0's) if the input is too low.
19
SCLK
DI
Serial Interface Shift Clock. The shift register latches SDI data on the
rising edges of SCLK. When LOAD is high SCLK is internally
disabled.
20
LOAD
DI
Serial Data Load. Rising edge of LOAD transfers data from shift
register to the addressed serial interface register. Load must be low
to enable shift register to read data from SDI.
21
SDI
DI
Serial Data Input. Input to serial interface shift register.
22
PowerDown
DI
Power Down Control. Same function as the "Chip PD" bit in the
Power Down register.
23
Reset
DI
Chip Reset. Same function as the "Reset" bit in the Reset register.
24
OK
DO
Serial Interface Check Bit. Goes high to indicate a successful serial
write operation.
26
REFin
AI
CDS Reference Input. Connect via capacitor to CCD reference supply.
27
CCDin
AI
CDS Video Input. Connect via capacitor to CCD video output.
28
Test1
AI
Test input.
Note:
1
Pin Type Codes: A = Analog, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
P = Power/Ground
XRD98L60
ADCinP
GND
SBLK
SPIX
CAL
CLAMP
ADCLK
VDD
GND
ADCinN
PGAoutN
PGAoutP
DB7
DB8
DB9
OVER
VDD
GND
SCLK
LOAD
SDI
PowerDown
RESET
OK
n/c
n/c
DB0
DB1
DB2
GND
DVDD
DB3
DB4
DB5
DB6
n/c
CapN
CapP
DAC0
DAC1
ExtRef
VDD
GND
Test2
Test1
CCDin
REFin
GND
1
37
48
47
46
45
44
43
42
41
40
39
38
25
36
26
27
28
29
30
31
32
33
34
35
13
14
15
16
17
18
19
20
21
22
23
24
12
2
3
4
5
6
7
8
9 10 11
PIN CONFIGURATIONS
48 Lead TQFP (7 x 7 x 1.4)
XRD98L60
4
Rev. P1.10
Preliminary
PIN DESCRIPTION (CONT'D)
Pin #
Name
Type (1)
Description
29
Test2
AI
Test Input.
32
ExtRef
AI
External Reference. Optional reference input for ADC.
33
DAC1
AO
DAC Output.
34
DAC0
AO
DAC Output.
35
CapP
A
Reference Bypass. Connect bypass capacitor for internal reference.
36
CapN
A
Reference Bypass. Connect bypass capacitor for internal reference.
37
PGAoutP
AO
PGA Positive Output. Activate by setting the "PGAout" bit in the
control register.
38
PGAoutN
AO
PGA Negative Output. Activate by setting the "PGAout" bit in the
control register.
39
ADCinP
AI
External ADC Positive Input. Activate by setting the "ADC in" bit in the
control register.
40
ADCinN
AI
External ADC Negative Input. Activate by setting the "ADC in" bit in
the control register.
43
ADCLK
DI
Optional External ADC Clock Input. Activate with the "ADC clk" bit in
the Clock register.
44
CLAMP
DI
DC Restore Clamp. Clamps CCDin & REFin pins to internal bias
voltage.
45
SPIX
DI
Sample Pixel CDS Clock. Controls sampling of the pixel video level.
46
SBLK
DI
Sample Black CDS Clock. Controls sampling of the pixel black
reference level.
47
CAL
DI
Calibration Control. Activates the Black Level Offset Calibration circuit.
6
GND
P
Digital Output ground.
7
DV
DD
P
Digital Output Power Supply. Must be less than or equal to V
DD
supply voltage.
17, 31, 42
V
DD
(3)
P
Analog Power Supply.
18, 30, 41
GND (3)
P
Analog Ground.
25, 48
GND (2)
P
Substrate Ground. Connect to analog ground plane.
1, 2, 12
N/C
These pins are not used.
Note:
1
Pin Type Codes: A = Analog, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
P = Power/Ground
XRD98L60
5
Rev. P1.10
Preliminary
ELECTRICAL CHARACTERISTICS
(preliminary information, specifications subject to change)
Parameter
Symbol
Min
Typ
Max
Units
Conditions
CDS
Maximum Reset Pulse
Vrst
500
mV
Reset Pulse - Reference level
(See fig. 23)
Maximum Input
Vpix
1.0
Volt
Reference level - signal level
(See fig. 24)
PGA
Minimum Gain
0
dB
Maximum Gain
32
dB
Gain Step Size
0.03
dB/lsb
10-bit PGA gain code
Differential Non-Linearity
-0.9
2
lsb
Guaranteed Monotonic
ADC
Resolution
10
bit
Differential Non-Linearity
DNL
0.5
lsb
Integral Non-Linearity
INL
2
lsb
Full Scale Input Range
1.0
2
Volt
ADC External Input Range
Vin
TBD
TBD
Volt
ADC External Reference
Vref
TBD
TBD
Volt
Guaranteed No Missing Codes
Offset Calibration
Cal Range (Input Referred)
Vblk
-100
600
mV
See figure 23
CAL Active Time
t
CAL
4
pixels
OB
1
pixels per line; "CalOpt"=0
CAL Active Time
t
CALOPT
8
pixels
OB
1
pixels per line; "CalOpt"=1
Black Level ADC Code Out
4
63
lsb
Offset Register
DC Restore Clamp
Clamp Active Time
t
CLAMP
4
pixels
OB
1
or dummy pixels per
line; "CalOpt"=0
Clamp Switch Impedance
TBD
Ohm
System
Maximum Conversion Rate
Fs1
40
MSPS
Standard Power Bias
Maximum Conversion Rate
Fs2
20
MSPS
Low Power Bias
System DNL
DNLs
0.8
lsb
Noise Level @ Min Gain
-54
dB
40 MSPS
Noise Level @ Max Gain
-50
dB
40 MSPS
Pipeline Delay (Latency)
8
cycles
Serial I/O Reset Delay
TBD
s
Note:
1
OB = Optically Black
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