2005 Fairchild Semiconductor Corporation
DS009893
www.fairchildsemi.com
July 1988
Revised March 2005
7
4
AC
2
99
74ACT299 8-I
nput Uni
versal
Shi
f
t/
S
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ora
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Regi
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r
74AC299 74ACT299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The AC/ACT299 is an 8-bit universal shift/storage register
with 3-STATE outputs. Four modes of operation are possi-
ble: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional out-
puts are provided for flip-flops Q
0
, Q
7
to allow easy serial
cascading. A separate active LOW Master Reset is used to
reset the register.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load
and store
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
ACT299 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74AC299SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC299SCX_NL
(Note 1)
M20B
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74AC299SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC299MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC299PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT299SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT299MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT299PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names
Description
CP
Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0
, S
1
Mode Select Inputs
MR
Asynchronous Master Reset
OE
1
, OE
2
3-STATE Output Enable Inputs
I/O
0
I/O
7
Parallel Data Inputs or
3-STATE Parallel Outputs
Q
0
, Q
7
Serial Outputs
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2
74AC299
74ACT299
Logic Symbols
IEEE/IEC
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
LOW-to-HIGH Transition
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flip-
flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S
0
and S
1
, as
shown in the Truth Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Inputs
Response
MR
S
1
S
0
CP
L
X
X
X
Asynchronous Reset; Q
0
Q
7
LOW
H
H
H
Parallel Load; I/O
n
o
Q
n
H
L
H
Shift Right; DS
0
o
Q
0
, Q
0
o
Q
1
, etc.
H
H
L
Shift Left, DS
7
o
Q
7
, Q
7
o
Q
6
, etc.
H
L
L
X
Hold
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4
74AC299
74ACT299
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT
circuits outside databook specifi-
cations.
DC Electrical Characteristics for AC
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V
20 mA
V
I
V
CC
0.5V
20 mA
DC Input Voltage (V
I
)
0.5V to V
CC
0.5V
DC Output Diode Current (I
OK
)
V
O
0.5V
20 mA
V
O
V
CC
0.5V
20 mA
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
DC Output Source or Sink Current (I
O
)
r
50 mA
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
r
50 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Junction Temperature (T
J
)
(PDIP)
140
q
C
Supply Voltage (V
CC
)
(Unless Otherwise Specified)
AC
2.0V to 6.0V
ACT
4.5V to 5.0V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
40
q
C to
85
q
C
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (
'
V/
'
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
3.0
1.5
2.1
2.1
V
OUT
0.1V
Input Voltage
4.5
2.25
3.15
3.15
V
or V
CC
0.1V
5.5
2.75
3.85
3.85
V
IL
Maximum LOW Level
3.0
1.5
0.9
0.9
V
OUT
0.1V
Input Voltage
4.5
2.25
1.35
1.35
V
or V
CC
0.1V
5.5
2.75
1.65
1.65
V
OH
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
V
I
OUT
50
P
A
5.5
5.49
5.4
5.4
V
IN
V
IL
or V
IH
3.0
2.56
2.46
V
I
OH
12 mA
4.5
3.86
3.76
I
OH
24 mA
5.5
4.86
4.76
I
OH
24 mA (Note 3)
V
OL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
V
I
OUT
50
P
A
5.5
0.001
0.1
0.1
V
IN
V
IL
or V
IH
3.0
0.36
0.44
I
OH
12 mA
4.5
0.36
0.44
V
I
OH
24 mA
5.5
0.36
0.44
I
OH
24 mA (Note 3)
I
IN
Maximum Input
5.5
r
0.1
r
1.0
P
A
V
I
V
CC
, GND
(Note 5)
Leakage Current
I
OLD
Minimum Dynamic
5.5
86
mA
V
OLD
1.65V Max
I
OHD
Output Current (Note 4)
75
mA
V
OHD
3.85V Min
I
CC
(Note 5)
Maximum Quiescent
5.5
4.0
40.0
P
A
V
IN
V
CC
or GND
Supply Current
5
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74
A
C
29
9
74ACT299
DC Electrical Characteristics for AC
(Continued)
Note 3: All outputs loaded; threshold on input associated with output under test.
Note 4: Maximum test duration 20 ms, one output loaded at a time.
Note 5: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
DC Electrical Characteristics for ACT
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
I
OZT
Maximum I/O Leakage Current
5.5
r
0.3
r
3.0
P
A
V
I
(OE)
V
IL
, V
IH
V
I
V
CC
, GND
V
O
V
CC
, GND
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
V
OUT
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
0.1V
V
IL
Maximum LOW Level
3.0
1.5
0.8
0.8
V
V
OUT
0.1V
Input Voltage
4.5
1.5
0.8
0.8
or V
CC
0.1V
V
OH
Minimum HIGH Level
4.5
4.49
4.4
4.4
V
I
OUT
50
P
A
5.5
5.49
5.4
5.4
V
IN
V
IL
or V
IH
4.5
0.0001
3.86
3.76
V
I
OH
24 mA
5.5
4.86
4.76
I
OH
24 mA (Note 6)
V
OL
Maximum LOW Level
4.5
0.001
0.1
0.1
V
I
OUT
50
P
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
24 mA
5.5
0.36
0.44
I
OL
24 mA (Note 6)
I
IN
Maximum Input Leakage Current
5.5
r
0.1
r
1.0
P
A
V
I
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
V
CC
2.1V
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
1.65V Max
I
OHD
Output Current (Note 7)
5.5
75
mA
V
OHD
3.85V Min
I
CC
Maximum Quiescent Supply Current
5.5
4.0
40.0
P
A
V
IN
V
CC
or GND
I
OZT
Maximum I/O
V
I
(OE)
V
IL
, V
IH
Leakage Current
5.5
r
0.3
r
3.0
P
A
V
I
V
CC
, GND
V
O
V
CC
, GND
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