ChipFind - документация

Электронный компонент: 74AC374SC

Скачать:  PDF   ZIP
2005 Fairchild Semiconductor Corporation
DS009959
www.fairchildsemi.com
November 1988
Revised March 2005
7
4
AC
3
74
74ACT374 O
c
t
a
l D-T
ype Fli
p
-
F
lop wit
h

3-
ST
A
T
E Output
s
74AC374 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Buffered positive edge-triggered clock
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
See 273 for reset version
s
See 377 for clock enable version
s
See 373 for transparent latch version
s
See 574 for broadside pinout version
s
See 564 for broadside pinout version with inverted
outputs
s
ACT374 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package
Package Description
Number
74AC374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC374SCX_NL
(Note 1)
M20B
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC374SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT374SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT374MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ACT374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT374MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
74AC374

74ACT374
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
LOW-to-HIGH Transition
Functional Description
The AC/ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O
0
O
7
3-STATE Outputs
Inputs
Outputs
D
n
CP
OE
O
n
H
L
H
L
L
L
X
X
H
Z
3
www.fairchildsemi.com
74
A
C
37
4


74ACT374
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics for AC
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V
20 mA
V
I
V
CC
0.5V
20 mA
DC Input Voltage (V
I
)
0.5V to V
CC
0.5V
DC Output Diode Current (I
OK
)
V
O
0.5V
20 mA
V
O
V
CC
0.5V
20 mA
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
)
r
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
r
50 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Junction Temperature (T
J
)
(PDIP)
140
q
C
Supply Voltage (V
CC
)
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
40
q
C to
85
q
C
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (
'
V/
'
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
3.0
1.5
2.1
2.1
V
OUT
0.1V
Input Voltage
4.5
2.25
3.15
3.15
V
or V
CC
0.1V
5.5
2.75
3.85
3.85
V
IL
Maximum LOW Level
3.0
1.5
0.9
0.9
V
OUT
0.1V
Input Voltage
4.5
2.25
1.35
1.35
V
or V
CC
0.1V
5.5
2.75
1.65
1.65
V
OH
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
V
I
OUT
50
P
A
5.5
5.49
5.4
5.4
V
IN
V
IL
or V
IH
3.0
2.56
2.46
I
OH
12 mA
4.5
3.86
3.76
V
I
OH
24 mA
5.5
4.86
4.76
I
OH
24 mA (Note 3)
V
OL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
V
I
OUT
50
P
A
5.5
0.001
0.1
0.1
V
IN
V
IL
or V
IH
3.0
0.36
0.44
I
OL
12 mA
4.5
0.36
0.44
V
I
OL
24 mA
5.5
0.36
0.44
I
OL
24 mA (Note 3)
I
IN
(Note 5)
Maximum Input Leakage Current
5.5
r
0.1
r
1.0
P
A
V
I
V
CC
, GND
I
OZ
Maximum 3-STATE Current
V
I
(OE)
V
IL
, V
IH
5.5
r
0.25
r
2.5
P
A
V
I
V
CC
, GND
V
O
V
CC
, GND
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
1.65V Max
I
OHD
Output Current (Note 4)
5.5
75
mA
V
OHD
3.85V Min
I
CC
(Note 5) Maximum Quiescent Supply Current
5.5
4.0
40.0
P
A
V
IN
V
CC
or GND
www.fairchildsemi.com
4
74AC374

74ACT374
DC Electrical Characteristics for ACT
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics
Note 8: Voltage Range 3.3 is 3.3V
r
0.3V
Voltage Range 5.0 is 5.0V
r
0.5V
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
V
OUT
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
0.1V
V
IL
Maximum LOW Level
4.5
1.5
0.8
0.8
V
V
OUT
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
0.1V
V
OH
Minimum HIGH Level
4.5
4.49
4.4
4.4
V
I
OUT
50
P
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
24 mA
5.5
4.86
4.76
I
OH
24 mA (Note 6)
V
OL
Maximum LOW Level
4.5
0.001
0.1
0.1
V
I
OUT
50
P
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
24 mA
5.5
0.36
0.44
I
OL
24 mA (Note 6)
I
IN
Maximum Input
5.5
r
0.1
r
1.0
P
A
V
I
V
CC
, GND
Leakage Current
I
OZ
Maximum
5.5
r
0.25
r
2.5
P
A
V
I
V
IL
, V
IH
3-STATE Current
V
O
V
CC
, GND
I
CCT
Maximum
5.5
0.6
1.5
mA
V
I
V
CC
2.1V
I
CC
/Input
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
1.65V Max
I
OHD
Output Current (Note 7)
5.5
75
mA
V
OHD
3.85V Min
I
CC
Maximum Quiescent
5.5
4.0
40.0
P
A
V
IN
V
CC
Supply Current
or GND
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
Symbol
Parameter
(V)
C
L
50 pF
CC
L
50 pF
Units
(Note 8)
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock
3.3
60
110
60
MHz
Frequency
5.0
100
155
100
t
PLH
Propagation Delay
3.3
3.0
11.0
13.5
1.5
15.5
ns
CP to O
n
5.0
2.5
8.0
9.5
1.5
10.5
t
PHL
Propagation Delay
3.3
2.5
10.0
12.5
2.0
14.0
ns
CP to O
n
5.0
2.0
7.0
9.0
1.5
10.0
t
PZH
Output Enable Time
3.3
3.0
9.5
11.5
1.5
13.0
ns
5.0
2.0
7.0
8.5
1.0
9.5
t
PZL
Output Enable Time
3.3
2.5
9.0
11.5
1.5
13.0
ns
5.0
2.0
6.5
8.5
1.0
9.5
t
PHZ
Output Disable Time
3.3
3.0
10.5
12.5
2.0
14.5
ns
5.0
2.0
8.0
11.0
2.0
12.5
t
PLZ
Output Disable Time
3.3
2.0
8.0
11.5
1.0
12.5
ns
5.0
1.5
6.5
8.5
1.0
10.0
5
www.fairchildsemi.com
74
A
C
37
4


74ACT374
AC Operating Requirements
Note 9: Voltage Range 3.3 is 3.3V
r
0.3V
Voltage Range 5.0 is 5.0V
r
0.5V
AC Electrical Characteristics
Note 10: Voltage Range 5.0 is 5.0V
r
0.5V
AC Operating Requirements
Note 11: Voltage Range 5.0 is 5.0V
r
0.5V
Capacitance
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Symbol
Parameter
(V)
C
L
50 pF
C
L
50 pF
Units
(Note 9)
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
3.3
2.0
5.5
6.0
ns
D
n
to CP
5.0
1.0
4.0
4.5
t
H
Hold Time, HIGH or LOW
3.3
1.0
1.0
1.0
ns
D
n
to CP
5.0
0
1.5
1.5
t
W
CP Pulse Width,
3.3
4.0
5.5
6.0
ns
HIGH or LOW
5.0
2.5
4.0
4.5
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Symbol
Parameter
(V)
C
L
50 pF
C
L
50 pF
Units
(Note 10)
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock
5.0
100
160
90
MHz
Frequency
t
PLH
Propagation Delay
5.0
2.0
8.5
10.0
2.0
11.5
ns
CP to O
n
t
PHL
Propagation Delay
5.0
2.0
8.0
9.5
1.5
11.0
ns
CP to O
n
t
PZH
Output Enable Time
5.0
2.0
8.0
9.5
1.5
10.5
ns
t
PZL
Output Enable Time
5.0
1.5
8.0
9.0
1.5
10.5
ns
t
PHZ
Output Disable Time
5.0
1.5
8.5
11.5
1.0
12.5
ns
t
PLZ
Output Disable Time
5.0
1.5
7.0
8.5
1.0
10.0
ns
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Symbol
Parameter
(V)
C
L
50 pF
C
L
50 pF
Units
(Note 11)
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0
1.0
5.5
5.5
ns
D
n
to CP
t
H
Hold Time, HIGH or LOW
5.0
0
1.5
1.5
ns
D
n
to CP
t
W
CP Pulse Width,
5.0
2.5
5.0
5.0
ns
HIGH or LOW
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
OPEN