2005 Fairchild Semiconductor Corporation
DS012006
www.fairchildsemi.com
February 1994
Revised March 2005
7
4LCX245
Low V
o
lt
age Bidi
rec
t
i
onal T
r
a
nsceiv
e
r w
i
th 5V T
o
l
e
ra
nt Input
s
and Output
s
74LCX245
Low Voltage Bidirectional Transceiver
with 5V Tolerant Inputs and Outputs
General Description
The LCX245 contains eight non-inverting bidirectional buff-
ers with 3-STATE outputs and is intended for bus oriented
applications. The device is designed for low voltage (2.5V
and 3.3V) V
CC
applications with capability of interfacing to
a 5V signal environment. The T/R input determines the
direction of data flow through the device. The OE input dis-
ables both the A and B ports by placing them in a high
impedance state.
The LCX245 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V to 3.6V V
CC
specifications provided
s
7.0 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
r
24 mA output drive (V
CC
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
s
Leadless DQFN Pb-Free package
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Note 3: DQFN package available in Tape and Reel only.
Note 4: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Number
Package Description
74LCX245WM
(Note 2)
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX245WMX_NL
(Note 4)
M20B
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX245SJ
(Note 2)
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX245BQX
(Note 3)
MLP020B
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm
74LCX245MSA
(Note 2)
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX245MTC
(Note 2)
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX245MTCX_NL
(Note 4)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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2
74LCX245
Logic Symbol
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Note 5: Unused bus terminals during HIGH Z State must be held
HIGH or LOW.
Connection Diagrams
Pin Assignments for SOIC,
SOP, SSOP, and TSSOP
Pin Assignment for DQFN
(Top Through View)
Logic Diagram
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A
0
A
7
Side A Inputs or 3-STATE Outputs
B
0
B
7
Side B Inputs or 3-STATE Outputs
Inputs
Outputs
OE
T/R
L
L
Bus B
0
B
7
Data to Bus A
0
A
7
L
H
Bus A
0
A
7
Data to Bus B
0
B
7
H
X
HIGH Z State on A
0
A
7
, B
0
B
7
(Note 5)
3
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7
4LCX245
Absolute Maximum Ratings
(Note 6)
Recommended Operating Conditions
(Note 8)
Note 6: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 7: I
O
Absolute Maximum Rating must be observed.
Note 8: Unused inputs or I/O pins must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
7.0
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
DC Output Voltage
0.5 to
7.0
Output in 3-STATE
V
0.5 to V
CC
0.5
Output in HIGH or LOW State (Note 7)
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
50
V
O
!
V
CC
I
O
DC Output Source/Sink Current
r
50
mA
I
CC
DC Supply Current per Supply Pin
r
100
mA
I
GND
DC Ground Current per Ground Pin
r
100
mA
T
STG
Storage Temperature
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.0
3.6
V
Data Retention
1.5
3.6
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
3-STATE
0
5.5
I
OH
/I
OL
Output Current
V
CC
3.0V to 3.6V
r
24
mA
V
CC
2.7V to 3.0V
r
12
V
CC
2.3V to 2.7V
r
8
T
A
Free-Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V to 2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
40
q
C to
85
q
C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.3 to 2.7
1.7
V
2.7 to 3.6
2.0
V
IL
LOW Level Input Voltage
2.3 to 2.7
0.7
V
2.7 to 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
100
P
A
2.3 to 3.6
V
CC
0.2
V
I
OH
8 mA
2.3
1.8
I
OH
12 mA
2.7
2.2
I
OH
18 mA
3.0
2.4
I
OH
24 mA
3.0
2.2
V
OL
LOW Level Output Voltage
I
OL
100
P
A
2.3 to 3.6
0.2
V
I
OL
8mA
2.3
0.6
I
OL
12 mA
2.7
0.4
I
OL
16 mA
3.0
0.4
I
OL
24 mA
3.0
0.55
I
I
Input Leakage Current
0
d
V
I
d
5.5V
2.3 to 3.6
r
5.0
P
A
I
OZ
3-STATE I/O Leakage
0
d
V
O
d
5.5V
2.3 to 3.6
r
5.0
P
A
V
I
V
IH
or V
IL
I
OFF
Power-Off Leakage Current
V
I
or V
O
5.5V
0
10
P
A
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4
74LCX245
DC Electrical Characteristics
(Continued)
Note 9: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
Conditions
V
CC
T
A
40
q
C to
85
q
C
Units
(V)
Min
Max
I
CC
Quiescent Supply Current
V
I
V
CC
or GND
2.3 to 3.6
10
P
A
3.6V
d
V
I
, V
O
d
5.5V (Note 9)
2.3 to 3.6
r
10
'
I
CC
Increase in I
CC
per Input
V
IH
V
CC
0.6V
2.3 to 3.6
500
P
A
Symbol
Parameter
T
A
40
q
C to
85
q
C, R
L
500
:
Units
V
CC
3.3V
r
0.3V
V
CC
2.7V
V
CC
2.5V
r
0.2V
C
L
50 pF
C
L
50 pF
C
L
30 pF
Min
Max
Min
Max
Min
Max
t
PHL
Propagation Delay
1.5
7.0
1.5
8.0
1.5
8.4
ns
t
PLH
A
n
to B
n
or B
n
to A
n
1.5
7.0
1.5
8.0
1.5
8.4
t
PZL
Output Enable Time
1.5
8.5
1.5
9.5
1.5
10.5
ns
t
PZH
1.5
8.5
1.5
9.5
1.5
10.5
t
PLZ
Output Disable Time
1.5
7.5
1.5
8.5
1.5
9.0
ns
t
PHZ
1.5
7.5
1.5
8.5
1.5
9.0
t
OSHL
Output to Output Skew
1.0
ns
t
OSLH
(Note 10)
1.0
Symbol
Parameter
Conditions
V
CC
T
A
25
q
C
Units
(V)
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
50 pF, V
IH
3.3V, V
IL
0V
3.3
0.8
V
C
L
30 pF, V
IH
2.5V, V
IL
0V
2.5
0.6
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
50 pF, V
IH
3.3V, V
IL
0V
3.3
0.8
V
C
L
30 pF, V
IH
2.5V, V
IL
0V
2.5
0.6
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
Open, V
I
0V or V
CC
7.0
pF
C
I/O
Input/Output Capacitance
V
CC
3.3V, V
I
0V or V
CC
8.0
pF
C
PD
Power Dissipation Capacitance
V
CC
3.3V, V
I
0V or V
CC
, f
10 MHz
25.0
pF
5
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7
4LCX245
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and t
rec
Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
r
= t
f
= 3ns)
Test
Switch
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
6V at V
CC
3.3V
r
0.3V
V
CC
x 2 at V
CC
2.5V
r
0.2V
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
r
0.3V
2.7V
2.5V
r
0.2V
V
mi
1.5V
1.5V
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
x
V
OL
0.3V
V
OL
0.3V
V
OL
0.15V
V
y
V
OH
0.3V
V
OH
0.3V
V
OH
0.15V
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6
74LCX245
Schematic Diagram
Generic for LCX Family
7
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7
4LCX245
Tape and Reel Specification
Tape Format for DQFN
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
BQX
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
Tape Size
A
B
C
D
N
W1
W2
12 mm
13.0
0.059
0.512
0.795
2.165
0.488
0.724
(330.0)
(1.50)
(13.00)
(20.20)
(55.00)
(12.4)
(18.4)
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8
74LCX245
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
9
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7
4LCX245
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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10
74LCX245
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Package Number MLP020B
11
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7
4LCX245
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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12
7
4LCX245
Lo
w
V
o
lt
age Bid
i
re
cti
onal T
r
a
nsceiv
e
r w
i
th 5V T
o
l
e
r
ant Input
s
and Output
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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