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Электронный компонент: 74VHCT138AM

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June 1997
Revised April 1999
7
4
VH
CT1
38A 3-
to-
8
Dec
oder/
D
em
ul
ti
pl
exer
1999 Fairchild Semiconductor Corporation
DS500014.prf
www.fairchildsemi.com
74VHCT138A
3-to-8 Decoder/Demultiplexer
General Description
The VHCT138A is an advanced high speed CMOS 3-to-8
DECODER fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
When the device is enabled, 3 Binary Select inputs (A
0
, A
1
and A
2
) determine which one of the outputs (O
0
O
7
) will go
LOW. When enable input E
3
is held LOW or either E
1
or E
2
is held HIGH, decoding function is inhibited and all outputs
go HIGH. E
3
, E
1
and E
2
inputs are provided to ease cas-
cade connection and for use as an address decoder for
memory systems. Protection circuits ensure that 0V to 7V
can be applied to the input pins without regard to the sup-
ply voltage and to the output pins with V
CC
=
0V. These cir-
cuits prevent device destruction due to mismatched supply
and input/output voltages. This device can be used to inter-
face 3V to 5V systems and two supply systems such as
battery backup.
Features
s
High Speed: t
PD
=
7.6 ns (typ) at V
CC
=
5V
s
Low power dissipation: I
CC
=
4
A (max.) at T
A
=
25
C
s
Power down protection is provided on all inputs and
outputs
s
Pin and function compatible with 74HCT138
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74VHCT138AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHCT138ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT138AMTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT138AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
A
0
A
2
Address Inputs
E
1
E
2
Enable Inputs
E
3
Enable Input
O
0
O
7
Outputs
www.fairchildsemi.com
2
7
4
VH
CT13
8A
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
E
1
E
2
E
3
A
0
A
1
A
2
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
3
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7
4
VH
CT1
38A
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 5)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: V
CC
=
0V.
Note 3: HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 4: V
OUT
<
GND, V
OUT
>
V
CC
(Outputs Active).
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
AC Electrical Characteristics
Note 6: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.)
=
C
PD
* V
CC
* f
IN
+
I
CC
.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
(Note 2)
-
0.5V to 7.0V
(Note 3)
-
0.5V to V
CC
+ 0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
(Note 4)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/GND Current (I
CC
)
75 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Supply Voltage (V
CC
)
4.5V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
(Note 3)
0V to V
CC
(Note 2)
0V to 5.5V
Operating Temperature (T
OPR
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
5.0V
0.5V
0
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level Input Voltage
4.5
-
5.5
2.0
2.0
V
V
IL
LOW Level Input Voltage
4.5
-
5.5
0.8
0.8
V
V
OH
HIGH Level
4.5
4.4
4.5
4.4
V
V
IN
=
V
IH
I
OH
=
-
50
A
Output Voltage
4.5
3.94
3.80
or V
IL
I
OH
=
-
8 mA
V
OL
LOW Level
4.5
0.0
0.1
0.1
V
V
IN
=
V
IH
I
OL
=
50
A
Output Voltage
4.5
0.36
0.44
or V
IL
I
OL
=
8 mA
I
IN
Input Leakage Current
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
20.0
A
V
IN
=
V
CC
or GND
I
CCT
Maximum I
CC/Input
5.5
1.35
1.50
mA
V
in
=
3.4V
other inputs
=
V
CC
or GND
I
OFF
Output Leakage Current
0
0.5
5.0
A
V
OUT
=
5.5V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
0.5
7.6
10.4
1.0
12.0
ns
C
L
=
15 pF
t
PHL
A
n
to O
n
8.1
11.4
1.0
13.0
C
L
=
50 pF
t
PLH
Propagation Delay
5.0
0.5
6.6
9.1
1.0
10.5
ns
C
L
=
15 pF
t
PHL
E
3
to O
n
7.1
10.1
1.0
11.5
C
L
=
50 pF
t
PLH
Propagation Delay
5.0
0.5
7.0
9.6
1.0
11.0
ns
C
L
=
15 pF
t
PHL
E
1
or E
2
to O
n
7.5
10.6
1.0
12.0
C
L
=
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
PD
Power Dissipation Capacitance
49
pF
(Note 6)
www.fairchildsemi.com
4
7
4
VH
CT13
8A
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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7
4
VH
CT1
38A
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16