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Электронный компонент: CD4071BCN

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October 1987
Revised January 1999
CD407
1BC

CD408
1BC

Quad 2
-
I
nput
OR Buf
f
e
re
d B
Seri
es Gat
e
Quad 2-
I
nput
AND

Buff
ered
B Se
rie
s
Gat
e
1999 Fairchild Semiconductor Corporation
DS005977.prf
www.fairchildsemi.com
CD4071BC CD4081BC
Quad 2-Input OR Buffered B Series Gate
Quad 2-Input AND Buffered B Series Gate
General Description
The CD4071BC and CD4081BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs protected against static discharge with diodes to
V
DD
and V
SS
.
Features
s
Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
s
5V10V15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
A at 15V over full
temperature range
Ordering Code:
Devices are also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
CD4071B
Top View
CD4081B
Top View
Order Number
Package Number
Package Description
CD4071BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
CD4071BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4081BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
CD4081BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
C
D
40
71BC
C
D
40
81BC
Schematic Diagrams
CD4071B
1
/
4
of device shown
J
=
A
+
B
Logical "1"
=
HIGH
Logical "0"
=
LOW
*All inputs protected by standard CMOS protection circuit.
CD4081B
1
/
4
of device shown
J
=
A B
Logical "1"
=
HIGH
Logical "0"
=
LOW
All inputs protected by standard CMOS protection circuit.
3
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CD407
1BC

CD408
1BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: All voltages measured with respect to V
SS
unless otherwise speci-
fied.
DC Electrical Characteristics
(Note 2)
CD4071BC/CD4081BC
Note 3: I
OH
and I
OL
are tested one output at a time.
AC Electrical Characteristics
(Note 4)
CD4071BC T
A
=
25
C, Input t
r
; t
f
=
20 ns, C
L
=
50 pF, R
L
=
200 k
, Typical temperature coefficient is 0.3%/
C
Note 4: AC Parameters are guaranteed by DC correlated testing.
Voltage at Any Pin
-
0.5V to V
DD
+
0.5V
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
V
DD
Range
-
0.5 V
DC
to
+
18 V
DC
Storage Temperature (T
S
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Operating Range (V
DD
)
3 V
DC
to 15 V
DC
Operating Temperature Range (T
A
)
CD4071BC, CD4081BC
-
40
C to
+
85
C
Symbol
Parameter
Conditions
-
40
C
+
25
C
+
85
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
=
5V
1
0.004
1
7.5
A
Current
V
DD
=
10V
2
0.005
2
15
A
V
DD
=
15V
4
0.006
4
30
A
V
OL
LOW Level
V
DD
=
5V
0.05
0
0.05
0.05
V
Output Voltage
V
DD
=
10V
|I
O
|
<
1
A
0.05
0
0.05
0.05
V
V
DD
=
15V
0.05
0
0.05
0.05
V
V
OH
HIGH Level
V
DD
=
5V
4.95
4.95
5
4.95
V
Output Voltage
V
DD
=
10V
|I
O
|
<
1
A
9.95
9.95
10
9.95
V
V
DD
=
15V
14.95
14.95
15
14.95
V
V
IL
LOW Level
V
DD
=
5V, V
O
=
0.5V
1.5
2
1.5
1.5
V
Input Voltage
V
DD
=
10V, V
O
=
1.0V
3.0
4
3.0
3.0
V
V
DD
=
15V, V
O
=
1.5V
4.0
6
4.0
4.0
V
V
IH
HIGH Level
V
DD
=
5V, V
O
=
4.5V
3.5
3.5
3
3.5
V
Input Voltage
V
DD
=
10V, V
O
=
9.0V
7.0
7.0
6
7.0
V
V
DD
=
15V, V
O
=
13.5V
11.0
11.0
9
11.0
V
I
OL
LOW Level Output
V
DD
=
5V, V
O
=
0.4V
0.52
0.44
0.88
0.36
mA
Current
V
DD
=
10V, V
O
=
0.5V
1.3
1.1
2.25
0.9
mA
(Note 3)
V
DD
=
15V, V
O
=
1.5V
3.6
3.0
8.8
2.4
mA
I
OH
HIGH Level Output
V
DD
=
5V, V
O
=
4.6V
-
0.52
-
0.44
-
0.88
-
0.36
mA
Current
V
DD
=
10V, V
O
=
9.5V
-
1.3
-
1.1
-
2.25
-
0.9
mA
(Note 3)
V
DD
=
15V, V
O
=
13.5V
-
3.6
-
3.0
-
8.8
-
2.4
mA
I
IN
Input Current
V
DD
=
15V, V
IN
=
0V
-
0.30
-
10
-
5
-
0.30
-
1.0
A
V
DD
=
15V, V
IN
=
15V
0.30
10
-
5
0.30
1.0
A
Symbol
Parameter
Conditions
Typ
Max
Units
t
PHL
Propagation Delay Time,
V
DD
=
5V
100
250
ns
HIGH-to-LOW Level
V
DD
=
10V
40
100
ns
V
DD
=
15V
30
70
ns
t
PLH
Propagation Delay Time,
V
DD
=
5V
90
250
ns
LOW-to-HIGH Level
V
DD
=
10V
40
100
ns
V
DD
=
15V
30
70
ns
t
THL
, t
TLH
Transition Time
V
DD
=
5V
90
200
ns
V
DD
=
10V
50
100
ns
V
DD
=
15V
40
80
ns
C
IN
Average Input Capacitance
Any Input
5
7.5
pF
C
PD
Power Dissipation Capacity
Any Gate
18
pF
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4
C
D
40
71BC
C
D
40
81BC
AC Electrical Characteristics
(Note 5)
CD4081BC T
A
=
25
C, Input t
r
; t
f
=
20 ns, C
L
=
50 pF, R
L
=
200 k
, Typical temperature coefficient is 0.3%/
C
Note 5: AC Parameters are guaranteed by DC correlated testing.
Typical Performance Characteristics
Typical Transfer
Characteristics
Typical Transfer
Characteristics
Typical Transfer
Characteristics
Typical Transfer
Characteristics
Symbol
Parameter
Conditions
Typ
Max
Units
t
PHL
Propagation Delay Time,
V
DD
=
5V
100
250
ns
HIGH-to-LOW Level
V
DD
=
10V
40
100
ns
V
DD
=
15V
30
70
ns
t
PLH
Propagation Delay Time,
V
DD
=
5V
120
250
ns
LOW-to-HIGH Level
V
DD
=
10V
50
100
ns
V
DD
=
15V
35
70
ns
t
THL
, t
TLH
Transition Time
V
DD
=
5V
90
200
ns
V
DD
=
10V
50
100
ns
V
DD
=
15V
40
80
ns
C
IN
Average Input Capacitance
Any Input
5
7.5
pF
C
PD
Power Dissipation Capacity
Any Gate
18
pF
5
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CD407
1BC

CD408
1BC
Typical Performance Characteristics
(Continued)