2002 Fairchild Semiconductor Corporation
DS006001
www.fairchildsemi.com
October 1987
Revised May 2002
CD454
1BC
Progr
am
mabl
e
T
i
m
e
r
CD4541BC
Programmable Timer
General Description
The CD4541BC Programmable Timer is designed with a
16-stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output control
logic, and a special power-on reset circuit. The special fea-
tures of the power-on reset circuit are first, no additional
static power consumption and second, the part functions
across the full voltage range (3V15V) whether power-on
reset is enabled or disabled.
Timing and the counter are initialized by turning on power,
if the power-on reset is enabled. When the power is
already on, an external reset pulse will also initialize the
timing and counter. After either reset is accomplished, the
oscillator frequency is determined by the external RC net-
work. The 16-stage counter divides the oscillator frequency
by any of 4 digitally controlled division ratios.
Features
s
Available division ratios 2
8
, 2
10
, 2
13
, or 2
16
s
Increments on positive edge clock transitions
s
Built-in low power RC oscillator (
2% accuracy over
temperature range and
10% supply and
3% over pro-
cessing @
<
10 kHz)
s
Oscillator frequency range
DC to 100 kHz
s
Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
s
Automatic reset initializes all counters when power turns
on
s
External master reset totally independent of automatic
reset operation
s
Operates at 2
n
frequency divider or single transition
timer
s
Q/Q select provides output logic level flexibility
s
Reset (auto or master) disables oscillator during reset-
ting to provide no active power dissipation
s
Clock conditioning circuit permits operation with very
slow clock rise and fall times
s
Wide supply voltage range--3.0V to 15V
s
High noise immunity--0.45 V
DD
(typ.)
s
5V10V15V parameter ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
A at 15V over full tempera-
ture range
s
High output drive (pin 8) min. one TTL load
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
N.C.--Not connected
Top View
Order Number
Package Number
Package Description
CD4541BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4541BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
C
D
45
41BC
Truth Table
Division Ratio Table
Operating Characteristics
With Auto Reset pin set to a "0" the counter circuit is initial-
ized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to
a "1". Both types of reset will result in synchronously reset-
ting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external
RC network, i.e.:
and R
S
2 R
tc
where R
S
10 k
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (2
8
, 2
10
, 2
13
, and
2
16
). The 2
n
counts as shown in the Division Ratio Table
represent the Q output of the Nth stage of the counter.
When A is "1", 2
16
is selected for both states of B.
However, when B is "0", normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i.e., effectively outputting 2
8
).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a "0" the Q output is a "0". Corre-
spondingly, when Q/Q select pin is set to a "1" the Q output
is a "1".
When the mode control pin is set to a "1", the selected
count is continually transmitted to the output. But, with
mode pin "0" and after a reset condition the RS flip-flop
resets (see Logic Diagram), counting commences and after
2
n
-
1
counts the RS flip-flop sets which causes the output to
change state. Hence, after another 2
n
-
1
counts the output
will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation.
Typical RC Oscillator
Characteristics
Solid Line
=
R
TC
=
56 k
, R
S
=
1 k
and C
=
1000 pF
f
=
10.2 kHz @ V
DD
=
10V and T
A
=
25
Dashed Line
=
R
TC
=
56 k
, R
S
=
120 k
and C
=
1000 pF
f
=
7.75 kHz @ V
DD
=
10V and T
A
=
25
RC Oscillator Frequency as a
Function of R
TC
and C
Line A: f as a function of C and (R
TC
=
56 k
; R
S
=
120k
Line B: f as a function of R
TC
and (C
=
100 pF; R
S
=
2 R
TC
Pin
State
0
1
5
Auto Reset Operating
Auto Reset Disabled
6
Timer Operational
Master Reset On
9
Output Initially Low
Output Initially High
after Reset
after Reset
10
Single Cycle Mode
Recycle Mode
Number of
Count
A
B
Counter Stages
2
n
n
0
0
13
8192
0
1
10
1024
1
0
8
256
1
1
16
65536
3
www.fairchildsemi.com
CD454
1BC
Operating Characteristics
(Continued)
Oscillator Circuit Using RC Configuration
Logic Diagram
V
DD
=
Pin 14
V
SS
=
Pin 7
www.fairchildsemi.com
4
C
D
45
41BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 2)
Note 3: I
OH
and I
OL
are tested one output at a time.
Supply Voltage (V
DD
)
-
0.5V to
+
18V
Input Voltage (V
IN
)
-
0.5V to V
DD
+
0.5V
Storage Temperature Range (T
S
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
)
(soldering, 10 seconds)
260
C
Supply Voltage (V
DD
)
3V to 15V
Input Voltage (V
IN
)
0 to V
DD
Operating Temperature Range
-
55
C to
+
125
C
Symbol
Parameter
Conditions
-
55
C
+
25
C
+
125
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
=
5V, V
IN
=
V
DD
or V
SS
5
0.005
5
150
A
V
DD
=
10V, V
IN
=
V
DD
or V
SS
10
0.010
10
300
V
DD
=
15V, V
IN
=
V
DD
or V
SS
20
0.015
20
600
V
OL
LOW Level Output Voltage
V
DD
=
5V
0.05
0
0.05
0.05
V
V
DD
=
10V
|I
O
|
<
1
A
0.05
0
0.05
0.05
V
DD
=
15V
0.05
0
0.05
0.05
V
OH
HIGH Level Output Voltage
V
DD
=
5V
4.95
4.95
5
4.95
V
V
DD
=
10V
|I
O
|
<
1
A
9.95
9.95
10
9.95
V
DD
=
15V
14.95
14.95
15
14.95
V
IL
LOW Level Input Voltage
V
DD
=
5V, V
O
=
0.5V or 4.5V
1.5
2
1.5
1.5
V
V
DD
=
10V, V
O
=
1.0V or 9.0V
3.0
4
3.0
3.0
V
DD
=
15V, V
O
=
1.5V or 13.5V
4.0
6
4.0
4.0
V
IH
HIGH Level Input Voltage
V
DD
=
5V, V
O
=
0.5V or 4.5V
3.5
3.5
3
3.5
V
V
DD
=
10V, V
O
=
1.0V or 9.0V
7.0
7.0
6
7.0
V
DD
=
15V, V
O
=
1.5V or 13.5V
11.0
11.0
9
11.0
I
OL
LOW Level Output Current
V
DD
=
5V, V
O
=
0.4V
2.85
2.27
3.6
1.6
mA
(Note 3)
V
DD
=
10V, V
O
=
0.5V
4.16
4.0
9.0
2.8
V
DD
=
15V, V
O
=
1.5V
19.3
15.6
34.0
10.9
I
OH
HIGH Level Output Current
V
DD
=
5V, V
O
=
2.5V
7.96
6.42
130
4.49
mA
(Note 3)
V
DD
=
10V, V
O
=
9.5V
4.19
3.38
8.0
2.37
V
DD
=
15V, V
O
=
13.5V
16.3
13.2
30.0
9.24
I
IN
Input Current
V
DD
=
15V, V
IN
=
0V
-
0.1
-
10
-
5
-
0.1
-
1.0
A
V
DD
=
15V, V
IN
=
15V
0.1
10
-
5
0.1
1.0
5
www.fairchildsemi.com
CD454
1BC
AC Electrical Characteristics
(Note 4)
T
A
=
25
C, C
L
=
50 pF (refer to test circuits)
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note:
AN-90.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
TLH
Output Rise Time
V
DD
=
5V
50
200
ns
V
DD
=
10V
30
100
V
DD
=
15V
25
80
t
THL
Output Fall Time
V
DD
=
5V
50
200
ns
V
DD
=
10V
30
100
V
DD
=
15V
25
80
t
PLH,
t
PHL
Turn-Off, Turn-On Propagation Delay,
V
DD
=
5V
1.8
4.0
s
Clock to Q (2
8
Output)
V
DD
=
10V
0.6
1.5
V
DD
=
15V
0.4
1.0
t
PHL,
t
PLH
Turn-On, Turn-Off Propagation Delay,
V
DD
=
5V
3.2
8.0
s
Clock to Q (2
16
Output)
V
DD
=
10V
1.5
3.0
V
DD
=
15V
1.0
2.0
t
WH(CL)
Clock Pulse Width
V
DD
=
5V
400
200
ns
V
DD
=
10V
200
100
V
DD
=
15V
150
70
f
CL
Clock Pulse Frequency
V
DD
=
5V
2.5
1.0
MHz
V
DD
=
10V
6.0
3.0
V
DD
=
15V
8.5
4.0
t
WH(R)
MR Pulse Width
V
DD
=
5V
400
170
ns
V
DD
=
10V
200
75
V
DD
=
15V
150
50
C
I
Average Input Capacitance
Any Input
5.0
7.5
pF
C
PD
Power Dissipation Capacitance (Note 5)
100
pF
PDF 
ZIP