www.fairchildsemi.com

Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.

REV. 1.0.6 6/26/01

Features

· Output programmable in 25mV steps from 1.05V to

1.825V using a dynamically programmable integrated
5-bit DAC

· Controls adjustable linears for Vclock (2.5V),

Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and
Vadj (1.2V nominal)

· Remote sense
· Programmable Active Droop

up to 200mV

· Drives N-Channel MOSFETs
· Overcurrent protection using MOSFET sensing
· Overvoltage protection including startup
· 85% efficiency typical at full load
· Integrated Power Good and Enable/Soft Start functions
· Meets Intel VRM8.5 specifications using minimum

number of external components

· 24 pin SOIC package

Applications

· Power supply for Pentium

III Platforms

· VRM for Pentium III processor
· Programmable multi-output power supply

Description

The FAN5056 is a synchronous mode DC-DC controller IC
which provides a highly accurate, programmable set of output
voltages for multi-voltage platforms such as the Intel Pentium III,
and provides a complete solution for all Intel VRM8.5 CPU
applications, and for other high-performance processors. The
FAN5056 features remote voltage sensing, independently
adjustable current limit, and a proprietary wide-range Pro-
grammable Active Droop

for optimal converter transient

response and VRM8.5 compliance. The FAN5056 uses a 5-bit
D/A converter to dynamically program the output voltage dur-
ing operation from 1.05V to 1.825V in 25mV steps. The
FAN5056 uses a high level of integration to deliver load cur-
rents in excess of 28A from a 5V source with minimal exter-
nal circuitry. Synchronous-mode operation offers optimum
efficiency over the entire specified output voltage range. An
on-board precision low TC reference achieves 0.8% voltage
regulation without expensive external components. The
FAN5056 includes linear regulator controllers for Vclock
(2.5V),Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V),
and Vadjustable (1.2V nominal) each adjustable with an
external divider. The FAN5056 also offers integrated functions

Block Diagram

VID3

VID2

VID1

VID0

GNDP

24
1

OSC

1.24V

Reference

Digital

Control

Power

Good

5-Bit

DAC

VID4

8 7 6 5 4

+5V

+12V

PWRGD

ENABLE/SS

VCC

GNDA

LODRV

HIDRV

VCCP

VCCA

+5V

REF

PWRGD,
OCL

+3.3V

+1.2V/Adj

+2.5V

OCL

VCCP

PWRGD, OCL

3.3/1.5V

FAN5056MV85

High Performance Programmable Synchronous
DC-DC Controller for Multi-Voltage Platforms

FAN5056MV85

PRODUCT SPECIFICATION

REV. 1.0.6 6/26/01

including open-collector Power Good, Output Enable/Soft
Start and current limiting, and is available in a 24 pin SOIC
package.

Pin Assignments

24
23
22
21
20
19
18
17
16
15
14
13

FAN5056

HIDRV

GNDA

VID4
VID3
VID2

VID1

VID0

VADJGATE

VADJFB

VCKGATE

VCKFB

VCCP
LODRV
GNDP
VCCA
VFB
DROOP
ILIM
PWRGD
SS/ENABLE
TYPEDET
VAGPGATE
VAGPFB

1
2
3
4
5
6
7
8
9
10
11
12

Pin Definitions

Pin Number

Pin Name

Pin Function Description

HIDRV

High Side FET Driver.

Connect this pin to the gate of an N-channel MOSFET. The

trace from this pin to the MOSFET gate should be <0.5".

High Side Driver Source and Low Side Driver Drain Switching Node.

Together

with DROOP and ILIM pins allows FET sensing for V

current.

GNDA

Analog Ground.

Return path for low power analog circuitry. This pin should be

connected to a low impedance system ground plane to minimize ground loops.

4-8

VID4-0

Voltage Identification Code Inputs.

These open collector/TTL compatible inputs

will program the output voltage over the ranges specified in Table 1. Pull-up
resistors are internal to the controller.

VADJGATE

Gate Driver for VADJ Transistor.

For Adjustable output.

VADJFB

Voltage Feedback for VADJ.

VCKGATE

Gate Driver for VCK Transistor.

For 2.5V output.

VCKFB

Voltage Feedback for VCK.

VAGPFB

Voltage Feedback for VAGP.

VAGPGATE

Gate Driver for VAGP Transistor.

For 3.3/1.5V output.

TYPEDET

Type Detect.

Sets 3.3V or 1.5V for AGP.

ENABLE/SS

Output Enable.

A logic LOW on this pin will disable all outputs. An internal current

source allows for open collector control. This pin also doubles as soft start for all
outputs.

PWRGD

Power Good Flag.

An open collector output that will be logic LOW if any output

voltage is not within ±14% of the nominal output voltage setpoint.

ILIM

Current Feedback.

Pin 18 is used in conjunction with pin 2 as the input for the

current feedback control loop. Layout of these traces is critical to system

performance. See Application Information for details.

DROOP

Droop Set.

Use this pin to set magnitude of active droop.

VFB

Vcc Voltage Feedback.

Pin 20 is used as the input for the V

voltage feedback

control loop. See Application Information for details regarding correct layout.

VCCA

Analog V

Connect to system 5V supply and decouple with a 0.1µF ceramic

capacitor.

PRODUCT SPECIFICATION

FAN5056MV85

REV. 1.0.6 6/26/01

Absolute Maximum Ratings

Note 1:

Component mounted on demo board in free air.

Recommended Operating Conditions

GNDP

Power Ground.

Return pin for high currents flowing in pin 24 (V

CCP

LODRV

Low Side FET Driver.

Connect this pin to the gate of an N-channel MOSFET

for synchronous operation. The trace from this pin to the MOSFET gate should be
<0.5".

VCCP

Power V

For all FET drivers. Connect to system 12V supply through a 33

, and

decouple with a 1µF ceramic capacitor.

Supply Voltage V

CCP

to GND

15V

Supply Voltage V

CCA

to GND

13.5V

Voltage Identification Code Inputs, VID0-VID4

VCCA

All Other Pins

13.5V

Junction Temperature, T

150°C

Storage Temperature

-65 to 150°C

Lead Soldering Temperature, 10 seconds

300°C

Thermal Resistance Junction-to-case,

75°C/W

Parameter

Conditions

Min.

Typ.

Max.

Units

Supply Voltage V

CCA

4.50

5.25

Input Logic HIGH

2.0

Input Logic LOW

0.8

Ambient Operating Temperature

°C

Output Driver Supply, V

CCP

10.8

13.2

Electrical Specifications

CCA

= 5V, V

CCP

= 12V, V

OUT

= 1.425V, and T

= +25°C using circuits in Figure 1, unless otherwise noted.)

The · denotes specifications which apply over the full operating temperature range.

Parameter

Conditions

Min.

Typ.

Max. Units

Regulator

Output Voltage

See Table I

FAN5056MV85

1.05

1.825

Output Current

Initial Voltage Setpoint

LOAD

= 0.8A, V

VID

= 1.425V

1.453

1.465

1.477

Output Temperature Drift

= 0 to 70°C, V

VID

= 1.425V

-6

Line Regulation

= 4.75V to 5.25V

+10

mV/V

Internal Droop Impedance

LOAD

= 0.8A to 30A

13.0

14.4

15.8

Maximum Programmable Droop

200

Output Ripple

20MHz BW, I

LOAD

= 28A

mVpk

Total Output Variation, Steady State

VID

= 1.425V

1.360

1.490

Pin Definitions

(Continued)

Pin Number

Pin Name

Pin Function Description

FAN5056MV85

PRODUCT SPECIFICATION

REV. 1.0.6 6/26/01

Notes:

1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is

measured at the converter's VFB sense point.

2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than

0.5m

trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal

performance.

3. Using the VFB pin for remote sensing of the converter's output at the load, and the appropriate droop, the converter will be

in compliance with Intel's VRM 8.5 specification. If Intel specifications on maximum plane resistance from the converter's
output capacitors to the CPU are met, the specifications at the capacitors will also be met.

4. PWRGD will be high only if BOTH the linears and the switcher conditions are met. PWRGD will be low if EITHER condition is met.

Total Output Variation, Transient

LOAD

= 0.8A to I

max

, V

VID

= 1.425V

1.335

1.515

Short Circuit Detect Current

µA

Efficiency

LOAD

= 18A, V

VID

= 1.425V

Output Driver Rise & Fall Time

See Figure 3

nsec

Output Driver Deadtime

See Figure 3

nsec

Duty Cycle

100

5V UVLO

3.76

4.24

12V UVLO

7.65

8.5

9.35

Adjustable Linear Regulator

Output Voltage

LOAD

1.188

1.212

1.236

Over Current Trip Level

VCLK Linear Regulator

Output Voltage

LOAD

2.375

2.5

2.625

Over Current Trip Level

VAGP Linear Regulator

Output Voltage

LOAD

2A, TYPEDET = 0V

1.425

1.5

1.575

Output Voltage

LOAD

2A, TYPEDET = OPEN

3.135

3.3

3.465

Over Current Trip Level

Common Functions

Oscillator Frequency

255

300

345

kHz

PWRGD Threshold

Switcher

Logic HIGH [V

VID

+ 85mV]

Logic LOW [V

VID

155mV]

·
·

88
80

112
120

PWRGD Delay Switcher

HIGH

LOW

µsec

PWRGD Hysteresis Switcher

PWRGD Threshold

Linear

Regulators

All Outputs

out

Electrical Specifications

(Continued)

CCA

= 5V, V

CCP

= 12V, V

OUT

= 1.425V, and T

= +25°C using circuits in Figure 1, unless otherwise noted.)

The · denotes specifications which apply over the full operating temperature range.

Parameter

Conditions

Min.

Typ.

Max. Units

FAN5056MV85

PRODUCT SPECIFICATION

REV. 1.0.6 6/26/01

Table 1. Output Voltage Programming Codes for FAN5056MV85

Note:

1. 0 = processor pin is tied to GND.

1 = processor pin is open

VID25mV

VID3

VID2

VID1

VID0

Nominal V

OUT

1.050V

1.075V

1.100V

1.125V

1.150V

1.175V

1.200V

1.225V

1.250V

1.275V

1.300V

1.325V

1.350V

1.375V

1.400V

1.425V

1.450V

1.475V

1.500V

1.525V

1.550V

1.575V

1.600V

1.625V

1.650V

1.675V

1.700V

1.725V

1.750V

1.775V

1.800V

1.825V

FAN5056MV85

PRODUCT SPECIFICATION

REV. 1.0.6 6/26/01

Table 3. FAN5056 Application Bill of Materials for Intel VRM8.5 Motherboards

(Components based on Worst Case Analysis--See Appendix for Details)

Notes:
1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with

Intel dI/dt requirements. L1 may be omitted if desired.

2. For 30A designs using the TO-220 MOSFETs, heatsinks with thermal resistance

< 20°C/W should be used. For designs

using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections,
refer to Applications Bulletins AB-8 and AB-15.

Reference

Manufacturer Part #

Quantity

Description

Requirements/Comments

AVX
TAJB475M010R5

4.7µF, 10V Capacitor

C2, C5

Panasonic
ECU-V1C105ZFX

1µF, 16V Capacitor

C3-4,C6

Panasonic
ECU-V1H104ZFX

100nF, 50V Capacitor

C7-9

Sanyo
6MV1000FA

1000µF, 6.3V
Electrolytic

Rubycon
16ZL1000M

1000µF, 16V
Electrolytic

RMS

= 2.3A

OUT

Rubycon
6.3ZL1500M

1500µF, 6.3V
Electrolytic

ESR

23m

Motorola
MBRD835L

8A Schottky Diode

Any

Optional

1.3µH, 10A Inductor

DCR ~ 6m

See Note 1.

Coiltronics
HC2-1R0

1.0µH, 34A Inductor

DCR ~ 1m

Fairchild
FDD6690A

N-Channel MOSFET

DS(ON)

= 17m

@ V

= 4.5V

See Note 2.

Fairchild
FDD6680A

N-Channel MOSFET

DS(ON)

= 13m

@ V

= 4.5V

See Note 2.

Q3-5

Fairchild
NDB4032L

N-Channel MOSFET

R1, R6

Any

R2-3

Any

4.7

Any

10K

Any

27.4K

Any

8.66K

Fairchild
FAN5056MV85M

DC/DC Controller

Test Parameters

Figure 2. Output Drive Timing Diagram

90%

HIDRV

LODRV

90%

10%

PRODUCT SPECIFICATION

FAN5056MV85

REV. 1.0.6 6/26/01

Application Information

The FAN5056 Controller

The FAN5056 is a programmable synchronous DC-DC con-
troller IC. When designed around the appropriate external
components, the FAN5056 can be configured to deliver more
than 28A of output current, as appropriate for Intel's
VRM8.5, and other processors. The FAN5056 functions as a
fixed frequency PWM step down regulator.

Main Control Loop

Refer to the FAN5056 Block Diagram on page 1. The
FAN5056 implements "summing mode control," which is
different from both classical voltage-mode and current-mode
control. It provides superior performance to either by allowing
a large converter bandwidth over a wide range of output loads.

The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
input from the DROOP (current feedback) and VFB (voltage
feedback) pins and sets up two controlling signal paths. The
first, the voltage control path, amplifies the difference
between the VFB signal and the reference voltage from the
DAC and presents the output to one of the summing amplifier
inputs. The second, current control path, takes the difference
between the DROOP and SW pins when the high-side
MOSFET is on, reproducing the voltage across the MOSFET
and thus the input current; it presents the resulting signal to
another input of the summing amplifier. These two signals are
then summed together. This output is then presented to a com-
parator looking at the oscillator ramp, which provides the
main PWM control signal to the digital control block.

The digital control block takes the analog comparator input
and the main clock signal from the oscillator to provide the
appropriate pulses to the HIDRV and LODRV output pins.
These two outputs control the external power MOSFETs.

There is an additional comparator in the analog control sec-
tion whose function is to set the point at which the FAN5056
current limit comparator disables the output drive signals to
the external power MOSFETs.

High Current Output Drivers

The FAN5056 contains two identical high current output
drivers that utilize high speed bipolar transistors in a push-
pull configuration. The drivers' power and ground are sepa-
rated from the chip's power and ground for switching noise
immunity. The power supply pin, V

CCP

, is supplied from an

external 12V source through a series resistor. The resulting
voltage is sufficient to provide the gate to source drive to the
external MOSFETs required in order to achieve a low
R

DS,ON

Internal Voltage Reference

The reference included in the FAN5056 is a precision band-
gap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Based on the reference is the output from an integrated 5-bit
DAC.

In the FAN5056MV85, the DAC monitors the 5 voltage
identification pins, VID0-4, and scales the voltage from
1.050V to 1.825V in 25mV steps according to Table I.

Power Good (PWRGD)

The FAN5056 Power Good function is designed in accor-
dance with VRM8.5 and DC-DC converter specifications
and provides a continuous voltage monitor on the VFB pin.
The circuit compares the VFB signal to the VREF voltage
and outputs an active-low interrupt signal to the CPU should
either of two conditions obtain: 1) any of the linear power
supply voltages deviate more than -20% from their nominal
setpoint; 2) The switching power supply output is more than
+14% from (V

VID

+ 80mV), or less than 14% from (V

VID

120mV). The Power Good flag provides no other control
function to the FAN5056.

Output Enable/Soft Start (ENABLE/SS)

The FAN5056 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the out-
put voltage. When disabled, the PWRGD output is in the low
state.

Even if an enable is not required in the circuit, this pin
should have attached a capacitor (typically 100nF) to soft-
start the switching.

Over-Voltage Protection

The FAN5056 continuously monitors the output voltage for
protection against over-voltage conditions. If the voltage at
the VFB pin exceeds approximately 2.5V, an OVP circuit
forces the low-side MOSFET on, over-riding all other
conditions. The OVP circuit remains active, and the low-side
MOSFET remains on, until the VFB voltage drops below
approximately 2.1V. The OVP circuit is functional even
during startup; thus, protection is provided even during
startup with a shorted high-side MOSFET.

Oscillator

The FAN5056 oscillator section uses a fixed frequency of
operation of 300KHz.

FAN5056MV85

PRODUCT SPECIFICATION

REV. 1.0.6 6/26/01

Design Considerations and Component
Selection

Additional information on design and component selection
may be found in Fairchild's Application Note 57.

MOSFET Selection

This application requires N-channel Logic Level Enhance-
ment Mode Field Effect Transistors. Desired characteristics
are as follows:

· Low Static Drain-Source On-Resistance, R

DS,ON

< 20m

(lower is better)

· Low gate drive voltage, V

= 4.5V rated

· Power package with low Thermal Resistance
· Drain-Source voltage rating > 15V.

The on-resistance (R

DS,ON

) is the primary parameter for

MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica-
tions Bulletin AB-8.

Inductor Selection

Choosing the value of the inductor is a trade-off between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
minimum to maximum range in order to either minimize rip-
ple or maximize transient performance. The first order equa-
tion (close approximation) for minimum inductance is:

where:
V

= Input Power Supply

out

= Output Voltage

f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
V

ripple

= Maximum peak to peak output ripple voltage budget.

The first order equation for maximum allowed inductance is:

where:
C

= The total output capacitance

= Maximum to minimum load transient current

= The output voltage tolerance budget allocated to load

transient
D

= Maximum duty cycle for the DC/DC converter (usu-

ally 95%).

Some margin should be maintained away from both L

min

and

max

. Adding margin by increasing L almost always adds

expense since all the variables are predetermined by system
performance except for C

, which must be increased to

increase L. Adding margin by decreasing L can be done by
purchasing capacitors with lower ESR. The FAN5056 pro-
vides significant cost savings for the newer CPU systems
that typically run at high supply current.

FAN5056 Short Circuit Current Characteristics

The FAN5056 protects against output short circuit on the
core supply by latching off both the high-side and low-side
MOSFETs. The FAN5056 short circuit current characteristic
includes a hysteresis function that prevents the DC-DC con-
verter from oscillating in the event of a short circuit. The
short circuit limit is set with the R

resistor, as given by the

formula

with I

Detect

50µA, ISC the desired current limit, and R

DS,on

the high-side MOSFET's on resistance. Remember to make
the R

large enough to include the effects of initial tolerance

and temperature variation on the MOSFET's R

DS,on

. Alter-

nately, use of a sense resistor in series with the source of the
MOSFET, as shown in Figure 6, eliminates this source of
inaccuracy in the current limit.

As an example, Figure 3 shows the typical characteristic of
the DC-DC converter circuit with two FDD6690A high-side
MOSFETs (R

= 17m

maximum at 25°C * 1.25 at 75°C

= 21.25m

each for a total of 10.6m) and a 6.19K R

Figure 3. FAN5056 Short Circuit Characteristic

The converter exhibits a normal load regulation characteris-
tic until the voltage across the MOSFET exceeds the internal
short circuit threshold of 50µA * 6.2K

= 310mV, which

occurs at 310mV/10.6m

= 29A. [Note that this current

limit level can be as high as 310mV/6.5m

= 48A, if the

MOSFET has typical R

DS,on

rather than maximum, and is at

25°C. This is the reason for using the external sense resistor.]
At this point, the internal comparator trips and signals the

min

(Vin V

out

)

out

ESR

ripple

max

(Vin V

out

) D

= 2C

DS, on

Detect

OUT

(V)

0 10 20 30 40 50

Output Current (A)

PRODUCT SPECIFICATION

FAN5056MV85

REV. 1.0.6 6/26/01

controller to reduce the converter's duty cycle to approxi-
mately 20%. This causes a drastic reduction in the output
voltage as the load regulation collapses into the short circuit
control mode. With a 4m

output short, the voltage is

reduced to 29A * 4m

= 116mV. The output voltage does

not return to its nominal value until the output current is
reduced to a value within the safe operating range for the
DC-DC converter.

Schottky Diode Selection

The application circuits of Figure 1 shows a Schottky diode,
D1, which is used as a free-wheeling diode to assure that the
body-diode in Q2 does not conduct when the upper MOS-
FET is turning off and the lower MOSFET is turning on. It is
undesirable for this diode to conduct because its high for-
ward voltage drop and long reverse recovery time degrades
efficiency, and so the Schottky provides a shunt path for the
current. Since this time duration is very short, the selection
criterion for the diode is that the forward voltage of the
Schottky at the output current should be less than the for-
ward voltage of the MOSFET's body diode.

Output Filter Capacitors

The output bulk capacitors of a converter help determine its
output ripple voltage and its transient response. It has
already been seen in the section on selecting an inductor that
the ESR helps set the minimum inductance, and the capaci-
tance value helps set the maximum inductance. For most
converters, however, the number of capacitors required is
determined by the transient response and the output ripple
voltage, and these are determined by the ESR and not the
capacitance value. That is, in order to achieve the necessary
ESR to meet the transient and ripple requirements, the
capacitance value required is already very large.

The most commonly used choice for output bulk capacitors
is aluminum electrolytics, because of their low cost and low
ESR. The only type of aluminum capacitor used should be
those that have an ESR rated at 100kHz. Consult Application
Bulletin AB-14 for detailed information on output capacitor
selection.

The output capacitance should also include a number of
small value ceramic capacitors placed as close as possible to
the processor; 0.1µF and 0.01µF are recommended values.

Input Filter

The DC-DC converter design may include an input inductor
between the system +5V supply and the converter input as
shown in Figure 5. This inductor serves to isolate the +5V
supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capac-
itors during power up. A value of 2.5µH is recommended.

It is necessary to have some low ESR aluminum electrolytic
capacitors at the input to the converter. These capacitors

deliver current when the high side MOSFET switches on.
Figure 4 shows 3 x 1000µF, but the exact number required
will vary with the speed and type of the processor. Capacitor
ripple current rating is a function of temperature, and so the
manufacturer should be contacted to find out the ripple cur-
rent rating at the expected operational temperature. For
details on the design of an input filter, refer to Applications
Bulletin AB-15.

Figure 4. Input Filter

Programmable Active Droop

The FAN5056 includes Programmable Active Droop

: as

the output current increases, the output voltage drops, and
the amount of this drop is user adjustable. This is done in
order to allow maximum headroom for transient response of
the converter. The current is typically sensed by measuring
the voltage across the R

DS,on

of the high-side MOSFET

during its on time, as shown in Figures 1 and 2.

To program the amount of droop, use the formula

where I

max

is the current at which the droop occurs, and

sense

is the resistance of the current sensor, either the source

resistor or the high-side MOSFET's on-resistance. For exam-
ple, to get 120mV of droop with a maximum output current
of 30A and a 10m

sense resistor, use R

= 14.4K

* 30A *

10m

/(120mV *3) = 12K. The value of the product

Imax*Rsense must be < 600mV for proper functioning of
the droop circuit. If this product is exceeded, a lower resis-
tance MOSFET must be used. Further details on use of the
Programmable Active Droop

may be found in Applications

Bulletin AB-24.

Remote Sense

The FAN5056 offers remote sense of the output voltage to
minimize the output capacitor requirements of the converter.
It is highly recommended that the remote sense pin, Pin 20,
be tied directly to the processor power pins, so that the
effects of power plane impedance are eliminated. Further
details on use of the remote sense feature of the FAN5056
may be found in Applications Bulletin AB-24.

2.5

µH

0.1

µF

1000

µF, 10V

Electrolytic

Vin

14.4K

max

sense

Droop

FAN5056MV85

PRODUCT SPECIFICATION

REV. 1.0.6 6/26/01

Adjusting the Linear Regulators' Output
Voltages

Any or all of the linear regulators' outputs may be adjusted
high to compensate for voltage drop along traces, as shown
in Figure 5.

Figure 5. Adjusting the Output Voltage of the

Linear Regulator

The resistor value should be chosen as

For example, to get the V

ADJ

voltage to be 1.50V instead of

1.20V, use R = 2K

* [(1.50/1.20) 1] = 500.

Using the FAN5056 for Vnorthbridge = 1.8V

Similarly, the FAN5056 can also be used to generate Vnorth-
bridge = 1.8V by utilizing the AGP regulator as shown in
Figure 5: tie the TYPEDET pin to ground, and use R = 399

Coppermine/Tualatin VTT

The adjustable regulator may be used for powering VTT
in systems in which either a Coppermine or a Tualatin
processor may be used, as shown in Figure 6.

Figure 6. Using VADJ to Generate VTT

PCB Layout Guidelines

· Placement of the MOSFETs relative to the FAN5056 is

critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the FAN5056 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difficult to
suppress.

· In general, all of the noisy switching lines should be kept

away from the quiet analog section of the FAN5056. That
is, traces that connect to pins 1, 2, 23, and 24 (HIDRV,
SW, LODRV and V

CCP

) should be kept far away from the

traces that connect to pins 3, 20 and 21.

· Place the 0.1µF decoupling capacitors as close to the

FAN5056 pins as possible. Extra lead length on these
reduces their ability to suppress noise.

· Each V

and GND pin should have its own via to the

appropriate plane. This helps provide isolation between
pins.

· Place the MOSFETs, inductor, and Schottky as close

together as possible for the same reasons as in the first
bullet above. Place the input bulk capacitors as close to
the drains of the high side MOSFETs as possible. In
addition, placement of a 0.1µF decoupling cap right on
the drain of each high side MOSFET helps to suppress
some of the high frequency switching noise on the input
of the DC-DC converter.

· Place the output bulk capacitors as close to the CPU as

possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter's performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.

· A PC Board Layout Checklist is available from Fairchild

Applications. Ask for Application Bulletin AB-11.

Additional Information

For additional information contact your local Fairchild
Semiconductor representative, or visit us at our web site
www.fairchildsemi.com.

VFB

VGATE

VOUT

10K

out

nom

VFB

VGATE

VTT

3.16K

2N7002

487

100

10K

AF36

PRODUCT SPECIFICATION

FAN5056MV85

REV. 1.0.6 6/26/01

Appendix

Worst-Case Formulae for the Calculation of
C

, C

out

, R5, R7 and R

offset

(Circuits similar

to Figure 1 only)

The following formulae design the FAN5056 for worst-case
operation, including initial tolerance and temperature depen-
dence of all of the IC parameters (initial setpoint, reference
tolerance and tempco, internal droop impedance, current
sensor gain), the initial tolerance and temperature depen-
dence of the MOSFET, and the ESR of the capacitors. The
following information must be provided:

S+

, the value of the positive static voltage limit;

S-

|, the absolute value of the negative static voltage limit;

T+

, the value of the positive transient voltage limit;

T-

|, the absolute value of the negative transient voltage

limit;

, the maximum output current;

nom

, the nominal output voltage;

, the input voltage (typically 5V);

rms

, the ripple current rating of the input capacitors, per cap

(2A for the Sanyo parts shown in this data sheet);

, the resistance of the current sensor (usually the MOSFET);

, the tolerance of the current sensor (usually about 67%

for MOSFET sensing, including temperature); and

ESR, the ESR of the output capacitors, per cap (44m

for

the Sanyo parts shown in this data sheet).

Number of capacitors needed for C

OUT

= the greater of:

Example: Suppose that the static limits are +89mV/-79mV,
transient limits are ±134mV, current I is 14.2A, and the nom-
inal voltage is 2.000V, using MOSFET current sensing. We
have V

S+

= 0.089, |V

S-

| = 0.079, V

T+

= |V

T-

| = 0.134, I

14.2, V

nom

= 2.000, and

= 1.67. We calculate:

Since Y > X, we choose Y, and round up to find we need 7
capacitors for C

OUT

A detailed explanation of this calculation may be found in
Applications Bulletin AB-24.

rms

.029 * V

nom

45 * 10

-6

* R

* (1 +

)

* 1K

S+

.014 * V

nom

.029

offset

18 * (V

S+

+ V

S-

.024 * V

nom

)

14400 * I

* R

* (1 +

) *1.1

R5 =

T-

+ V

S+

.024 * V

nom

ESR * I

X =

18 * R5 * 1.1

14400 * I

* R

T+

S+

2.000

14.2

3.47

4 caps

3.48K

18 * (0.089 + 0.079 .024 * 2.000)

14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1

10.5K

45 * 10

-6

14.2 * 0.020 * (1 + 0.67)

*1000 = 15.8

0.29 + 2.000

0.089 .014 * 2.000 .029

offset

3.57

0.134 + 0.089 .024 * 2.00

0.044 * 14.2

6.14

18 * 3640 * 1.1

14400 * 14.2 * 0.020

0.134 0.089

0.044 * 14.2

PRODUCT SPECIFICATION

FAN5056MV85

REV. 1.0.6 6/26/01

Mechanical Dimensions

24 Lead SOIC

.093

.104

2.35

2.65

Symbol

Inches

Min.

Max.

Min.

Max.

Millimeters

Notes

.004

.012

0.10

0.30

.020

0.51

.013

0.33

.009

.013

0.23

0.32

.290

.299

7.36

7.60

.394

.419

10.00

10.65

.010

.020

0.25

0.51

.050 BSC

1.27 BSC

.016

.050

0.40

1.27

ccc

.004

0.10

.599

.614

15.20

15.60

Notes:

Dimensioning and tolerancing per ANSI Y14.5M-1982.

"D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).

"L" is the length of terminal for soldering to a substrate.

Terminal numbers are shown for reference only.

"C" dimension does not include solder finish thickness.

Symbol "N" is the maximum number of terminals.

ccc C

LEAD COPLANARITY

SEATING
PLANE

h x 45

FAN5056MV85

PRODUCT SPECIFICATION

6/26/01 0.0m 005

Stock#DS30005056MV85

2001 Fairchild Semiconductor Corporation

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Ordering Information

Product Number

Description

Package

FAN5056MV85

VRM8.5

24 pin SOIC

Document Outline

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Document Outline

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