November 1997
FDC634P
P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
Absolute Maximum Ratings
T
A
= 25C unless otherwise note
Symbol Parameter
FDC634P
Units
V
DSS
Drain-Source Voltage
-20
V
V
GSS
Gate-Source Voltage - Continuous
8
V
I
D
Drain Current - Continuous
(Note 1a)
-3.5
A
- Pulsed
-11
P
D
Maximum Power Dissipation
(Note 1a)
1.6
W
(Note 1b)
0.8
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
30
C/W
FDC634P Rev.C
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as cellular phone and
notebook computer power management and other battery
powered circuits where high-side switching, and low in-line
power loss are needed in a very small outline surface
mount package.
-3.5 A, -20 V. R
DS(ON)
= 0.080
@ V
GS
= -4.5 V
R
DS(ON)
= 0.110
@ V
GS
= -2.5 V.
SuperSOT
TM
-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SOIC-16
SOT-23
SuperSOT
TM
-8
SO-8
SOT-223
SuperSOT
TM
-6
D
D
D
S
D
G
SuperSOT -6
TM
.634
pin
1
3
5
6
4
1
2
3
1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 A
-20
V
BV
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
I
D
= -250 A, Referenced to 25
o
C
-29
mV /
o
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -16 V, V
GS
= 0 V
-1
A
T
J
= 55
o
C
-10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 8 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -8 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 A
-0.4
-0.6
-1
V
V
GS(th)
/
T
J
Gate Threshold VoltageTemp.Coefficient
I
D
= -250 A, Referenced to 25
o
C
2.1
mV /
o
C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -4.5 V, I
D
= -3.5 A
0.07
0.08
T
J
= 125
o
C
0.099
0.13
V
GS
= -2.5 V, I
D
= -3.1 A
0.093
0.11
I
D(on)
On-State Drain Current
V
GS
= -4.5 V, V
DS
= -5 V
-10
A
g
FS
Forward Transconductance
V
DS
= -10 V, I
D
= -3.5 A
6.5
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= -10 V, V
GS
= 0 V,
665
pF
C
oss
Output Capacitance
f = 1.0 MHz
270
pF
C
rss
Reverse Transfer Capacitance
70
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -5 V, I
D
= -1 A,
8
16
ns
t
r
Turn - On Rise Time
V
GS
= -4.5 V, R
GEN
= 6
24
38
ns
t
D(off)
Turn - Off Delay Time
50
80
ns
t
f
Turn - Off Fall Time
29
45
ns
Q
g
Total Gate Charge
V
DS
= -5 V, I
D
= -3.5 A,
9.5
13
nC
Q
gs
Gate-Source Charge
V
GS
= -4.5 V
1.3
nC
Q
gd
Gate-Drain Charge
2.2
nC
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
Continuous Source Diode Current
-1.3
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
-0.75
-1.2
V
T
J
= 125
o
C
-0.6
-1
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
a. 78
o
C/W when mounted on a 1 in
2
pad of 2oz Cu in FR-4 board.
b. 156
o
C/W when mounted on a minimum pad of 2oz Cu in FR-4 board.
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
FDC634P Rev.C
FDC634P Rev.C
0
1
2
3
4
5
0
3
6
9
12
15
-V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN-SOURCE CURRENT (A)
V = -4.5V
GS
DS
D
-2.5
-2.0
-3.0
-1.5
-3.5
0
3
6
9
12
15
0.8
1
1.2
1.4
1.6
1.8
2
-I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = -2.0 V
GS
D
R , NORMALIZED
DS(ON)
-3.5
-4.5
-2.5
-3.0
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 3. On-Resistance Variation
with Temperature.
Figure 5. Transfer Characteristics.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0.0001
0.001
0.01
0.1
1
15
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0V
GS
SD
S
Figure 6. Body Diode Forward Voltage
Variation with Source Current and
Temperature.
Figure 4. On Resistance Variation with
Gate-To- Source Voltage.
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
R , NORMALIZED
DS(ON)
V = -4.5V
GS
I = -3.5A
D
1
2
3
4
5
0.05
0.1
0.15
0.2
0.25
-V , GATE TO SOURCE VOLTAGE (V)
GS
R , ON-RESISTANCE (OHM)
DS(ON)
I = -1.8A
D
T = 125C
J
25C
0
0.5
1
1.5
2
2.5
3
0
3
6
9
12
15
-V , GATE TO SOURCE VOLTAGE (V)
-I , DRAIN CURRENT (A)
V = -5.0V
DS
GS
D
T = -55C
J
125C
25C
FDC634P Rev.C
Figure 10. Single Pulse Maximum Power
Dissipation.
0.1
0.2
0.5
1
2
5
10
30
30
80
200
600
800
1200
2000
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0 V
GS
C
oss
C
rss
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical And Thermal Characteristics
0
2
4
6
8
10
0
1
2
3
4
5
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
V = -5V
DS
-10V
I = -3.5A
D
-15V
0.1
0.2
0.5
1
2
5
10
20
40
0.01
0.03
0.1
0.3
1
5
10
20
- V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN CURRENT (A)
RDS(ON) LIMIT
D
A
DC
DS
1s
100ms
10ms
1ms
V = -4.5V
SINGLE PULSE
R = See Note 1b
T = 25C
JA
GS
A
100us
0.01
0.1
1
10
100
300
0
1
2
3
4
5
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =See note 1b
T = 25C
JA
A
0.0001
0.001
0.01
0.1
1
10
100
300
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
r(t), NORMALIZED EFFECTIVE
Duty Cycle, D = t / t
1
2
R (t) = r(t) * R
R = See Note 1b
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
Figure 11. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.
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