2004 Fairchild Semiconductor Corporation
November 2004
FDP8874 Rev. A2
FDP887
4
FDP8874
N-Channel PowerTrench
MOSFET
30V, 114A, 5.3m
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r
DS(ON)
and fast switching speed.
Applications
DC/DC converters
Features
r
DS(ON)
= 5.3m
, V
GS
= 10V, I
D
= 40A
r
DS(ON)
= 6.6m
, V
GS
= 4.5V, I
D
= 40A
High performance trench technology for extremely low
r
DS(ON)
Low gate charge
High power and current handling capability
MOSFET Maximum Ratings
T
C
= 25C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
30
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
114
A
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Note 1)
Continuous (T
C
= 25
o
C, V
GS
= 4.5V) (Note 1)
102
A
Continuous (T
amb
= 25
o
C, V
GS
= 10V, with R
JA
= 62
o
C/W)
16
A
Pulsed
Figure 4
A
E
AS
Single Pulse Avalanche Energy (Note 2)
105
mJ
P
D
Power dissipation
110
W
Derate above 25
o
C
0.73
W/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 175
o
C
R
JC
Thermal Resistance Junction to Case TO-220
1.36
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-220 ( Note 3)
62
o
C/W
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDP8874
FDP8874
TO-220AB
Tube
N/A
50 units
FDP8874
FDP8874_NL (Note 4)
TO-220AB
Tube
N/A
50 units
D
G
S
TO-220AB
FDP SERIES
DRAIN
DRAIN
GATE
SOURCE
(FLANGE)
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
Electrical Characteristics
T
C
= 25C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1: Package current limitation is 80A.
2: Starting T
J
= 25C, L = 51uH, I
AS
= 64A, V
DD
= 27V, V
GS
= 10V.
3: Pulse width = 100s.
4: FDP8874_NL is lead free product. FDP8874_NL marking will appear on the label.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
30
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24V
-
-
1
A
V
GS
= 0V
T
C
= 150
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
=
20V
-
-
100
nA
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
1.2
-
2.5
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 40A, V
GS
= 10V
-
0.0036 0.0053
I
D
= 40A, V
GS
= 4.5V
-
0.0045 0.0066
I
D
= 40A, V
GS
= 10V,
T
J
= 175
o
C
-
0.0062 0.0090
C
ISS
Input Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
-
3130
-
pF
C
OSS
Output Capacitance
-
590
-
pF
C
RSS
Reverse Transfer Capacitance
-
345
-
pF
R
G
Gate Resistance
V
GS
= 0.5V, f = 1MHz
-
1.9
-
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 15V
I
D
= 40A
I
g
= 1.0mA
-
56
72
nC
Q
g(5)
Total Gate Charge at 5V
V
GS
= 0V to 5V
-
30
38
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 1V
-
3.0
4.0
nC
Q
gs
Gate to Source Gate Charge
-
9.0
-
nC
Q
gs2
Gate Charge Threshold to Plateau
-
6.0
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
11
-
nC
t
ON
Turn-On Time
V
DD
= 15V, I
D
= 40A
V
GS
= 4.5V, R
GS
= 4.7
-
-
207
ns
t
d(ON)
Turn-On Delay Time
-
10
-
ns
t
r
Rise Time
-
128
-
ns
t
d(OFF)
Turn-Off Delay Time
-
44
-
ns
t
f
Fall Time
-
31
-
ns
t
OFF
Turn-Off Time
-
-
112
ns
V
SD
Source to Drain Diode Voltage
I
SD
= 40A
-
-
1.25
V
I
SD
= 20A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
= 40A, dI
SD
/dt = 100A/
s
-
-
32
ns
Q
RR
Reverse Recovered Charge
I
SD
= 40A, dI
SD
/dt = 100A/
s
-
-
18
nC
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
Typical Characteristics
T
C
= 25C unless otherwise noted
Figure 1. Normalized Power Dissipation vs Case
Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
T
C
, CASE TEMPERATURE (
o
C)
PO
W
E
R DI
SSI
P
A
T
I
O
N
M
U
L
T
I
P
L
I
ER
0
0
25
50
75
100
175
0.2
0.4
0.6
0.8
1.0
1.2
125
150
0
25
50
75
100
125
25
50
75
100
125
150
175
I
D
, DRAIN CURRENT
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
CURRENT LIMITED
BY PACKAGE
V
GS
= 10V
V
GS
= 4.5V
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
2
t, RECTANGULAR PULSE DURATION (s)
Z
JC
, NORM
AL
IZ
ED
TH
ERM
A
L I
M
PED
AN
CE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
100
1000
50
I
DM
,
P
E
AK CURRE
NT
(
A
)
t, PULSE WIDTH (s)
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 4.5V
V
GS
= 10V
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics
T
C
= 25C unless otherwise noted
0.1
1
10
100
1000
1
10
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DR
AIN
C
URRENT
(
A
)
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
10
s
1ms
DC
100
s
10ms
1
10
100
0.01
0.1
1
10
500
100
I
AS
, A
V
AL
ANCHE CURR
ENT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
40
80
120
160
2.0
2.5
3.0
3.5
4.0
I
D
, DRAIN CURR
ENT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= -55
o
C
T
J
= 25
o
C
0
40
80
120
160
0
0.2
0.4
0.6
0.8
1.0
I
D
, DRAIN CUR
RENT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 10V
V
GS
= 4V
V
GS
= 3V
V
GS
= 5V
2
4
6
8
10
12
2
4
6
8
10
I
D
= 1A
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 40A
r
DS(
O
N)
, DRAIN T
O
SOURCE
ON RE
SIST
ANCE
(
m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-80
-40
0
40
80
120
160
200
NORM
AL
IZ
ED DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RES
I
ST
ANCE
V
GS
= 10V, I
D
= 40A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
Typical Characteristics
T
C
= 25C unless otherwise noted
0.4
0.6
0.8
1.0
1.2
-80
-40
0
40
80
120
160
200
V
GS
= V
DS
, I
D
= 250
A
NORM
AL
IZ
E
D
GA
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
T
HRE
SHOL
D V
O
L
T
A
GE
0.90
0.95
1.00
1.05
1.10
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
NORM
AL
IZ
ED DRAIN T
O
S
O
URCE
I
D
= 250
A
BRE
AKDO
WN V
O
L
T
A
GE
100
1000
0.1
1
10
30
5000
C, CA
P
A
CIT
ANCE
(
p
F
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
=
C
GD
0
2
4
6
8
10
0
10
20
30
40
50
60
V
GS
,
GA
T
E
T
O
SOURCE
V
O
L
T
A
GE (
V
)
Q
g
, GATE CHARGE (nC)
V
DD
= 15V
I
D
= 40A
I
D
= 1A
WAVEFORMS IN
DESCENDING ORDER:
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit
Figure 18.
Gate Charge Waveforms
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
V
DD
Q
g(TH)
V
GS
= 1V
Q
gs2
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
Q
g(5)
V
GS
= 5V
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
PSPICE Electrical Model
.SUBCKT FDP8874 2 1 3 ; rev May 2004
Ca 12 8 2.3e-9
Cb 15 14 2.25e-9
Cin 6 8 2.9e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33.3
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 8.5e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.7e-9
RLgate 1 9 85
RLdrain 2 5 10
RLsource 3 7 27
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.7e-3
Rgate 9 20 1.9
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 1.7e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=4.1E-12 IKF=10 N=1.01 RS=2e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=1.22e-9 M=0.57 TT=3e-12 XTI=3)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.12e-9 IS=1e-30 N=10 M=0.42)
.MODEL MmedMOD NMOS (VTO=2 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9)
.MODEL MstroMOD NMOS (VTO=2.5 KP=390 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.72 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=7e-3 TC2=3.8e-6)
.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-4 TC2=2.5e-6)
.MODEL RvthresMOD RES (TC1=-2.4e-3 TC2=-8e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
SABER Electrical Model
rev May 2004
template FDP8874 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4.1e-12,ikf=10,nl=1.01,rs=2e-3,trs1=8e-4,trs2=2e-7,cjo=1.22e-9,m=0.57,tt=3e-12,xti=3)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.12e-9,isl=10e-30,nl=10,m=0.42)
m..model mmedmod = (type=_n,vto=2,kp=9,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.5,kp=390,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.72,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)
c.ca n12 n8 = 2.3e-9
c.cb n15 n14 = 2.25e-9
c.cin n6 n8 = 2.9e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 33.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 8.5e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9
res.rlgate n1 n9 = 85
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7
res.rdrain n50 n16 = 1.7e-3, tc1=7e-3,tc2=3.8e-6
res.rgate n9 n20 = 1.9
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.7e-3, tc1=1e-4,tc2=2.5e-6
res.rvthres n22 n8 = 1, tc1=-2.4e-3,tc2=-8e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2004 Fairchild Semiconductor Corporation
FDP8874 Rev. A2
FDP887
4
PSPICE Thermal Model
REV 23 May 2004
FDP8874T
CTHERM1 TH 6 1.9e-3
CTHERM2 6 5 2.8e-3
CTHERM3 5 4 3.5e-3
CTHERM4 4 3 3.6e-3
CTHERM5 3 2 4.0e-3
CTHERM6 2 TL 1.6e-2
RTHERM1 TH 6 3.8e-2
RTHERM2 6 5 5.0e-2
RTHERM3 5 4 1.0e-1
RTHERM4 4 3 1.8e-1
RTHERM5 3 2 3.5e-1
RTHERM6 2 TL 3.7e-1
SABER Thermal Model
SABER thermal model FDP8874T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.9e-3
ctherm.ctherm2 6 5 =2.8e-3
ctherm.ctherm3 5 4 =3.5e-3
ctherm.ctherm4 4 3 =3.6e-3
ctherm.ctherm5 3 2 =4.0e-3
ctherm.ctherm6 2 tl =1.6e-2
rtherm.rtherm1 th 6 =3.8e-2
rtherm.rtherm2 6 5 =5.0e-2
rtherm.rtherm3 5 4 =1.0e-1
rtherm.rtherm4 4 3 =1.8e-1
rtherm.rtherm5 3 2 =3.5e-1
rtherm.rtherm6 2 tl =3.7e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
DISCLAIMER
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
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This datasheet contains the design specifications for
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changes at any time without notice in order to improve
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This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
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