March 1998

FDR856P

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

Features

Absolute Maximum Ratings

= 25

C unless other wise noted

Symbol

Parameter

FDR856P

Units

DSS

Drain-Source Voltage

-30

GSS

Gate-Source Voltage - Continuous

±20

Maximum Drain Current - Continuous

(Note 1a)

-5.1

- Pulsed

-50

Maximum Power Dissipation

(Note 1a)

1.8

(Note 1b)

(Note 1c)

0.9

STG

Operating and Storage Temperature Range

-55 to 150

°C

THERMAL CHARACTERISTICS
R

Thermal Resistance, Junction-to-Ambient

(Note 1a)

°C/W

Thermal Resistance, Junction-to-Case

(Note 1)

°C/W

FDR856P Rev.B

SOT-23

SuperSOT

-8

SOIC-16

SO-8

SOT-223

SuperSOT

-6

- 6.3 A, -30 V, R

DS(ON)

=0.025

@ V

= -10 V

DS(ON)

=0.040

@ V

= -4.5 V.

SuperSOT

-8 package:

small footprint (40% less than SO-8);low profile (1mm
thick);maximum power comperable to SO-8.

High density cell design for extremely low R

DS(ON)

SuperSOT

-8 P-Channel enhancement mode power field

effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as battery powered circuits or
portable electronics where low in-line power loss, fast
switching and resistance to transients are needed.

SuperSOT -8

pin

856P

Electrical Characteristics (

= 25

C unless otherwise noted )

Symbol

Parameter

Conditions

Min

Typ

Max

Units

OFF CHARACTERISTICS
BV

DSS

Drain-Source Breakdown Voltage

= 0 V, I

= -250 µA

-30

DSS

Breakdown Voltage Temp. Coefficient

= -250 µA, Referenced to 25

-15

mV /

DSS

Zero Gate Voltage Drain Current

= -24 V, V

= 0 V

-1

µA

= 55°C

-10

µA

GSSF

Gate - Body Leakage, Forward

= -20 V, V

= 0 V

-100

GSSR

Gate - Body Leakage, Reverse

= -20 V, V

= 0 V

-100

ON CHARACTERISTICS

(Note 2)

GS(th)

Gate Threshold Voltage

= V

, I

= -250 µA

-1

-1.5

-3

GS(th)

Gate Threshold Voltage Temp. Coefficient

= -250 µA, Referenced to 25

mV /

DS(ON)

Static Drain-Source On-Resistance

= -10 V, I

= -6.3 A

0.022

0.025

=125°C

0.03

0.042

= -4.5 V, I

= -5 A

0.033

0.04

D(ON)

On-State Drain Current

= -10 V, V

= -5 V

-50

Forward Transconductance

= -10 V, I

= -6.3 A

DYNAMIC CHARACTERISTICS
C

iss

Input Capacitance

= -15 V, V

= 0 V,

f = 1.0 MHz

1370

oss

Output Capacitance

740

rss

Reverse Transfer Capacitance

220

SWITCHING CHARACTERISTICS

(Note 2)

D(on)

Turn - On Delay Time

= -15 V, I

= -1 A

Turn - On Rise Time

= -10 V , R

= 6

D(off)

Turn - Off Delay Time

100

Turn - Off Fall Time

130

160

Total Gate Charge

= -15 V, I

= -6.3 A,

Gate-Source Charge

= -10 V

3.8

Gate-Drain Charge

8.7

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I

Maximum Continuous Drain-Source Diode Forward Current

-1.3

Drain-Source Diode Forward Voltage

= 0 V, I

= -1.3 A

(Note 2)

-0.73

-1.2

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is guaranteed by

design while R

is determined by the user's board design.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

FDR856P Rev.B

c. 125

C/W on a 0.003 in

pad

of 2oz copper.

b. 105

C/W on a 0.02 in

pad of 2oz copper.

a. 50

C/W on a 0.5 in

pad of 2oz copper.

FDR856P Rev.B

0.5

1.5

2.5

-V , DRAIN-SOURCE VOLTAGE (V)

- I , DRAIN-SOURCE CURRENT (A)

-4.5V

-2.5V

-4.0V

-5.5V

-3.5V

-3.0V

V = -10V

Typical Electrical Characteristics

Figure 1. On-Region Characteristics

Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage

-50

-25

100

125

150

0.6

0.8

1.2

1.4

1.6

T , JUNCTION TEMPERATURE (°C)

DRAIN-SOURCE ON-RESISTANCE

R , NORMALIZED

DS(ON)

V = -10V

I = -6.3A

Figure 3. On-Resistance Variation with

Temperature

-V , GATE TO SOURCE VOLTAGE (V)

- I , DRAIN CURRENT (A)

V = -5V

T = -55°C

125°C

25°C

Figure 5 . Transfer Characteristics.

Figure 6 . Body Diode Forward Voltage

Variation with Source

Current and Temperature.

0.025

0.05

0.075

0.1

0.125

-V , GATE TO SOURCE VOLTAGE (V)

R , ON-RESISTANCE (OHM)

DS(ON)

I = -3A

T = 125°C

T = 25°C

Figure 4 . On Resistance

Variation with

Gate-to-Source Voltage.

0.5

1.5

2.5

- I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

V = -3.5 V

R , NORMALIZED

DS(on)

-10V

-4.5V

-4.0V

-7.0V

-5.0V

-5.5V

0.2

0.4

0.6

0.8

1.2

0.0001

0.001

0.01

0.1

-V , BODY DIODE FORWARD VOLTAGE (V)

-I , REVERSE DRAIN CURRENT (A)

25°C

-55°C

V = 0V

T = 125°C

FDR856P Rev.B

Figure 10. Single Pulse Maximum Power

Dissipation.

Figure 8. Capacitance Characteristics.

Figure 7. Gate Charge Characteristics.

Figure 9. Maximum Safe Operating Area

Typical Electrical Characteristics

(continued)

0.0001

0.001

0.01

0.1

100

300

0.01

0.02

0.03

0.05

0.1

0.2

0.3

0.5

t , TIME (sec)

TRANSIENT THERMAL RESISTANCE

Single Pulse

D = 0.5

0.1

0.05

0.02

0.01

0.2

Duty Cycle, D = t / t

R (t) = r(t) * R

R = 135

°C/W

T - T = P * R (t)

P(pk)

r(t), NORMALIZED EFFECTIVE

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.

Q , GATE CHARGE (nC)

-V , GATE-SOURCE VOLTAGE (V)

V = -5V

-15V

I = -6.3A

-10V

0.1

0.3

100

200

500

1000

2000

4000

-V , DRAIN TO SOURCE VOLTAGE (V)

CAPACITANCE (pF)

iss

f = 1 MHz
V = 0 V

oss

rss

0.1

0.2

0.5

0.01

0.05

0.5

-V , DRAIN-SOURCE VOLTAGE (V)

-I , DRAIN CURRENT (A)

RDS(ON) LIMIT

V = -10V

SINGLE PULSE

R = 135°C/W

T = 25°C

100ms

10ms

1ms

10s

100us

0.0001

0.001

0.01

0.1

100 300

SINGLE PULSE TIME (SEC)

POWER (W)

SINGLE PULSE

R = 135°C/W

T = 25°C

SSOT-8 Packaging
Configuration: Figure 1.0

Components

Lead er Tape
500mm mi nimum or
62 empty poc kets

Traile r Tape
300mm mi nimum or
38 empty pockets

SSOT-8 Tape Leader and Trailer
Configuration: Figur e 2.0

Cover Tape

Carrier Tape

Note/Comments

Packaging Option

SSOT-8 Packaging Information

Standard

(no

f l ow c ode )

D84Z

Packaging type

Reel Size

TNR

13" D ia

TNR

7" Dia

Qty per Reel/Tube/Bag

3,000

500

Box Dimension (mm)

343x64x343

184x187x47

Max qty per Box

6,000

1,000

Weight per unit (gm)

0.0416

Weight per Reel (kg)

0.5615

0.0980

184mm x 187mm x 47mm

Pizza Box fo r D84Z Option

F63TNR
Label

F63TNR Labe l

F63TNR Labe l sa mpl e

343mm x 342mm x 64mm

Intermediate bo x fo r Standar d

and L 99Z Opti ons

F63TNR
Label

LOT: CBVK741B019

FSID: FDR835N

D/C1: D9842 QTY1:

SPEC REV:

SPEC:

QTY: 3000

D/C2:

QTY2:

CPN:

N/F: F (F63TNR)3

SSOT-8 Unit Orientation

F852
831N

Pin 1

F63TNR Labe l

Anti static Cover Tape

Customized La bel

Static Dissi pat ive

Emboss ed Carrier Tape

Packaging Description:

SSOT-8 parts are shipped in tape. The carrier tape is
made from a di ssipat ive (carbo n filled) po ly carbon ate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film ,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped w ith
3,000 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 unit s per 7" or
177cm diameter reel. This and some other options are
further described in the Packagin g Information table.

These full reels are in di vidu ally barcod e labeled and
placed inside a standard intermediate box (ill ustrated in
figure 1.0) made of recyclable corrugated brow n paper.
One box contains two reels maximum. And t hese boxes
are placed ins ide a barcode labeled shipp ing bo x whic h
comes in di fferent sizes depend in g on t he nu mber of parts
shippe d.

SuperSOT

-8 Tape and Reel Data and Package Dimensions

August 1999, Rev. C

1998 Fairchild Semiconductor Corporation

Dimensions are in millimeter

Pkg type

SSOT-8

(12mm)

4.47
+/-0.10

5.00
+/-0.10

12.0
+/-0.3

1.55
+/-0.05

1.50
+/-0.10

1.75
+/-0.10

10.25
mi n

5.50
+/-0.05

8.0
+/-0.1

4.0
+/-0.1

1.37
+/-0.10

0.280
+/-0.150

9.5
+/-0.025

0.06
+/-0.02

Dimensions are in inches and millimeters

Tape Size

Reel

Option

Dim A

Dim B

Dim C

Dim D

Dim N

Dim W1

Dim W2

Dim W3 (LSL-USL)

12mm

7" Dia

7.00
177.8

0.059
1.5

512 +0.020/-0.008
13 +0.5/-0.2

0.795
20.2

5.906
150

0.488 +0.078/-0.000
12.4 +2/0

0.724
18.4

0.469 0.606
11.9 15.4

12mm

13" Dia

13.00
330

0.059
1.5

512 +0.020/-0.008
13 +0.5/-0.2

0.795
20.2

7.00
178

0.488 +0.078/-0.000
12.4 +2/0

0.724
18.4

0.469 0.606
11.9 15.4

See detail AA

Dim A

max

13" Diameter Option

7" Diameter Option

Dim A

Max

See detail AA

W2 max Measured at Hub

W1 Measured at Hub

Dim N

Dim D

min

Dim C

B Min

DETAIL AA

Notes : A0, B0, and K0 di mens ions are deter mined with r espec t to t he EIA/Jedec RS-481

rotati ona l and lateral movement requi remen ts (see sketches A, B, and C).

20 deg maximum component rotation

0.5mm
maximum

Sketch C (Top View)

Component lateral movement

Typical
component
cavity
center line

20 deg maximum

Typical
component
center line

Sketch B (Top View)

Component Rotation

Sketch A (Si de or Front Sectional View)

Component Rotation

User Direction of Feed

SSOT-8 Embossed Carrier Tape
Configuration: Figur e 3.0

SSOT-8 Reel Configuration: Figur e 4.0

SuperSOT

-8 Tape and Reel Data and Package Dimensions, continued

July 1999, Rev. C

TRADEMARKS

ACExTM
CoolFETTM
CROSSVOLTTM
E

CMOS

FACTTM
FACT Quiet SeriesTM
FAST

FASTrTM
GTOTM
HiSeCTM

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Formative or
In Design

First Production

Full Production

Not In Production

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

SyncFETTM
TinyLogicTM
UHCTM
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ISOPLANARTM
MICROWIRETM
POPTM
PowerTrench
QFETTM
QSTM
Quiet SeriesTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8

Rev. D

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