2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev.1.0.3
Features
Single Chip 700V Sense FET Power Switch
Precision Fixed Operating Frequency (134kHz)
Advanced Burst-Mode operation Consumes under 0.1W
at 265Vac and no load (FSD210 only)
Internal Start-up Switch and Soft Start
Under Voltage Lock Out (UVLO) with Hysteresis
Pulse by Pulse Current Limit
Over Load Protection (OLP)
Internal Thermal Shutdown Function (TSD)
Auto-Restart Mode
Frequency Modulation for EMI
FSD200 does not require an auxiliary bias winding
Applications
Charger & Adaptor for Mobile Phone, PDA & MP3
Auxiliary Power for White Goods, PC, C-TV & Monitor
Description
The FSD200 and FSD210 are integrated Pulse Width Modu-
lators (PWM) and Sense FETs specially designed for high
performance off-line Switch Mode Power Supplies (SMPS)
with minimal external components. Both devices are mono-
lithic high voltage power switching regulators which com-
bine an LDMOS Sense FET with a voltage mode PWM
control block. The integrated PWM controller features in-
clude: a fixed oscillator with frequency modulation for re-
duced EMI, Under Voltage Lock Out (UVLO) protection,
Leading Edge Blanking (LEB), optimized gate turn-on/turn-
off driver, thermal shut down protection (TSD), temperature
compensated precision current sources for loop compensa-
tion and fault protection circuitry. When compared to a dis-
crete MOSFET and controller or RCC switching converter
solution, the FSD200 and FSD210 reduce total component
count, design size, weight and at the same time increase effi-
ciency, productivity, and system reliability. The FSD200
eliminates the need for an auxiliary bias winding at a small
cost of increased supply power. Both devices are a basic plat-
form well suited for cost effective designs of flyback convert-
ers.
Table 1. Notes: 1. Typical continuous power in a non-ven-
tilated enclosed adapter measured at 50
C ambient. 2.
Maximum practical continuous power in an open frame
design at 50
C ambient. 3. 230 VAC or 100/115 VAC with
doubler.
Typical Circuit
Figure 1. Typical Flyback Application using FSD210
Figure 2. Typical Flyback Application using FSD200
OUTPUT POWER TABLE
PRODUCT
230VAC
15%
(3)
85-265VAC
Adapter
(1)
Open
Frame
(2)
Adapter
(1)
Open
Frame
(2)
FSD210
5W
7W
4W
5W
FSD200
5W
7W
4W
5W
FSD210M
5W
7W
4W
5W
FSD200M
5W
7W
4W
5W
Drain
Source
Vstr
Vfb
Vcc
PWM
AC
IN
DC
OUT
Drain
Source
Vstr
Vfb
Vcc
PWM
AC
IN
DC
OUT
FSD210, FSD200
Green Mode Fairchild Power Switch (FPS
TM
)
FSD210, FSD200
2
Internal Block Diagram
Figure 3. Functional Block Diagram of FSD210
Figure 4. Functional Block Diagram of FSD200 showing internal high voltage regulator
8
5
UVLO
Voltage
Ref
H
Vstr
Vcc
Internal
Bias
L
Rsense
Iover
S/S
3mS
4
1, 2, 3
7
OSC
S
R
Q
TSD
S
R
Q
LEB
OLP
Reset
A/R
DRIVER
Frequency
Modulation
5uA
250uA
Vck
Vth
SFET
Drain
GND
Vfb
BURST
V
SD
V
BURST
8.7/6.7V
Rsense
Iover
S/S
3mS
4
1, 2, 3
7
OSC
S
R
Q
TSD
S
R
Q
LEB
OLP
Reset
A/R
DRIVER
Frequency
Modulation
5uA
250uA
Vck
Vth
SFET
Drain
GND
Vfb
BURST
V
SD
V
BURST
7V
8
5
UVLO
Voltage
Ref.
HV/REG
INTERNAL
BIAS
ON/OFF
Vstr
Vcc
FSD210, FSD200
3
Pin Definitions
Pin Configuration
Figure 5. Pin Configuration (Top View)
Pin Number
Pin Name
Pin Function Description
1, 2, 3
GND
Sense FET source terminal on primary side and internal control ground.
4
Vfb
The feedback voltage pin is the inverting input to the PWM comparator with
nominal input levels between 0.5Vand 2.5V. It has a 0.25mA current source
connected internally while a capacitor and opto coupler are typically
connected externally. A feedback voltage of 4V triggers overload protection
(OLP). There is a time delay while charging between 3V and 4V using an
internal 5uA current source, which prevents false triggering under transient
conditions but still allows the protection mechanism to operate under true
overload conditions.
5
Vcc
FSD210
Positive supply voltage input. Although connected to an auxiliary
transformer winding, current is supplied from pin 8 (Vstr) via an internal
switch during startup (see Internal Block Diagram section). It is not until Vcc
reaches the UVLO upper threshold (8.7V) that the internal start-up switch
opens and device power is supplied via the auxiliary transformer winding.
FSD200
This pin is connected to a storage capacitor. A high voltage regulator
connected between pin 8 (Vstr) and this pin, provides the supply voltage to
the FSD200 at startup and when switching during normal operation. The
FSD200 eliminates the need for auxiliary bias winding and associated
external components.
7
Drain
The Drain pin is designed to connect directly to the primary lead of the
transformer and is capable of switching a maximum of 700V. Minimizing the
length of the trace connecting this pin to the transformer will decrease
leakage inductance.
8
Vstr
The startup pin connects directly to the rectified AC line voltage source for
both the FSD200 and FSD210. For the FSD210, at start up the internal
switch supplies internal bias and charges an external storage capacitor
placed between the Vcc pin and ground. Once this reaches 8.7V, the
internal current source is disabled. For the FSD200, an internal high voltage
regulator provides a constant supply voltage.
1
2
3
4
5
7
8
GND
GND
GND
Vfb
Vstr
Drain
Vcc
7-DIP
7-LSOP
FSD210, FSD200
4
Absolute Maximum Ratings
(Ta=25
C unless otherwise specified)
Thermal Impedance
Note:
1. Free standing without heat sink.
2. Measured on the GND pin close to plastic interface.
3. Soldered to 100mm
2
copper clad.
4. Soldered to 300mm
2
copper clad.
Parameter
Symbol
Value
Unit
Maximum Supply Voltage (FSD200)
V
CC,MAX
10
V
Maximum Supply Voltage (FSD210)
V
CC,MAX
20
V
Input Voltage Range
V
FB
-
0.3 to V
STOP
V
Operating Junction Temperature.
T
J
+150
C
Operating Ambient Temperature
T
A
-
25 to +85
C
Storage Temperature Range
T
STG
-
55 to +150
C
Parameter
Symbol
Value
Unit
7DIP
Junction-to-Ambient Thermal
JA
(1)
74.07
(3)
C/W
JA
(1)
60.44
(4)
C/W
Junction-to-Case Thermal
JC
(2)
22.00
C/W
7LSOP
Junction-to-Ambient Thermal
JA
(1)
-
C/W
JA
(1)
-
C/W
Junction-to-Case Thermal
JC
(2)
-
C/W
FSD210, FSD200
5
Electrical Characteristics
(Ta=25
C unless otherwise specified)
Note:
1. These parameters, although guaranteed, are not 100% tested in production
2. This parameter is derived from characterization
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Sense FET SECTION
Drain-Source Breakdown Voltage
BV
DSS
V
CC
= 0V, I
D
= 100
A
700
-
-
V
Startup Voltage (Vstr) Breakdown
BV
STR
700
-
-
V
Off-State Current
I
DSS
V
DS
= 560V
-
-
100
A
On-State Resistance
R
DS(ON)
Tj = 25
C, I
D
= 25mA
-
28
32
Tj = 100
C, I
D
= 25mA
-
42
48
Rise Time
T
R
V
DS
= 325V, I
D
= 50mA
-
100
-
ns
Fall Time
T
F
V
DS
= 325V, l
D
= 25mA
-
50
-
ns
CONTROL SECTION
Output Frequency
F
OSC
Tj = 25
C
126
134
142
kHz
Output Frequency Modulation
F
MOD
Tj = 25
C
-
4
-
kHz
Feedback Source Current
I
FB
Vfb = 0V
0.22
0.25
0.28
mA
Maximum Duty Cycle
D
MAX
Vfb = 3.5V
60
65
70
%
Minimum Duty Cycle
D
MIN
Vfb = 0V
0
0
0
%
UVLO Threshold Voltage (FSD200)
V
START
6.3
7
7.7
V
V
STOP
After turn on
5.3
6
6.7
V
UVLO Threshold Voltage (FSD210)
V
START
8.0
8.7
9.4
V
V
STOP
After turn on
6.0
6.7
7.4
V
Supply Shunt Regulator (FSD200)
V
CCREG
-
-
7
-
V
Internal Soft Start Time
T
S/S
-
3
-
ms
BURST MODE SECTION
Burst Mode Voltage
V
BURH
Tj = 25
C
0.58
0.64
0.7
V
V
BURL
0.5
0.58
0.64
V
Hysteresis
-
60
-
mV
PROTECTION SECTION
Drain to Source Peak Current Limit
I
OVER
0.275 0.320 0.365
A
Current Limit Delay
(1)
T
CLD
Tj = 25
C
-
220
-
ns
Thermal Shutdown Temperature (Tj)
(1)
T
SD
125
145
160
C
Shutdown Feedback Voltage
V
SD
-
3.5
4.0
4.5
V
Feedback Shutdown Delay Current
I
DELAY
Vfb = 4.0V
3
5
7
A
Leading Edge Blanking Time
(2)
T
LEB
200
-
-
ns
TOTAL DEVICE SECTION
Operating Supply Current (FSD200)
I
OP
Vcc = 7V
-
600
-
A
Operating Supply Current (FSD210)
I
OP
Vcc = 11V
-
700
-
A
Start Up Current (FSD200)
I
START
Vcc = 0V
-
1
1.2
mA
Start Up Current (FSD210)
I
START
Vcc = 0V
-
700
900
A
Vstr Supply Voltage
Vcc = 0V
20
-
-
V
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