August 1996
NDT410EL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
___________________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C unless otherwise noted
Symbol
Parameter
NDT410EL
Units
V
DSS
Drain-Source Voltage
100
V
V
GSS
Gate-Source Voltage
20
V
I
D
Drain Current - Continuous
(Note 1a)
2.1
A
- Pulsed
10
P
D
Maximum Power Dissipation
(Note 1a)
3
W
(Note 1b)
1.3
(Note 1c)
1.1
T
J
,T
STG
Operating and Storage Temperature Range
-65 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
42
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
12
C/W
* Order option J23Z for cropped center drain lead.
NDT410EL Rev. B1
Power SOT N-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance, provide superior
switching performance, and withstand high energy pulses
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls, and
other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
2.1A 100V. R
DS(ON)
= 0.25
@ V
GS
= 5V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
D
D
S
G
D
S
G
1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE AVALANCHE RATINGS
(Note 2)
W
DSS
Single Pulse Drain-Source Avalanche Energy V
DD
= 50 V, I
D
= 10A
15
mJ
I
AR
Maximum Drain-Source Avalanche Current
10
A
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
100
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 80 V, V
GS
= 0 V
1
A
T
J
= 55C
10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
1
1.5
2
V
T
J
= 125C
0.65
1.1
1.5
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 5 V, I
D
= 2.1 A
0.2
0.25
T
J
= 125C
0.37
0.5
I
D(on)
On-State Drain Current
V
GS
= 5 V, V
DS
= 5 V
10
A
g
FS
Forward Transconductance
V
DS
= 10 V, I
D
= 2.1 A
6
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
528
pF
C
oss
Output Capacitance
85
pF
C
rss
Reverse Transfer Capacitance
20
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= 50 V, I
D
= 2.1 A,
V
GEN
= 5 V, R
GEN
= 25
9
20
ns
t
r
Turn - On Rise Time
72
120
ns
t
D(off)
Turn - Off Delay Time
49
80
ns
t
f
Turn - Off Fall Time
47
80
ns
Q
g
Total Gate Charge
V
DS
= 80 V, I
D
= 2.1 A, V
GS
= 5 V
10
16
nC
Q
gs
Gate-Source Charge
1.5
nC
Q
gd
Gate-Drain Charge
5.6
nC
NDT410EL Rev. B1
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
2.3
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 2.3 A
(Note 2)
1.3
V
t
rr
Reverse Recovery Time
V
GS
= 0 V, I
S
= 2.3 A, dI
F
/dt = 100A/s
150
ns
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
JA
(
t
)
=
T
J
-
T
A
R
JC
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
@
T
J
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 95
o
C/W when mounted on a 0.04 in
2
pad of 2oz copper.
c. 110
o
C/W when mounted on a 0.006 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDT410EL Rev. B1
1a
1b
1c
NDT410EL Rev. B1
0
1
2
3
4
5
6
0
2
4
6
8
10
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
6.0
5.0
4.0
3.5
2.5
V = 10V
GS
DS
D
3.0
J
R , NORMALIZED
DS(ON)
-50
-25
0
2 5
50
7 5
100
125
150
175
0.5
1
1.5
2
2.5
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
V = 5V
GS
I = 2.1A
D
-50
-25
0
25
50
75
100
125
150
175
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE (V)
J
V , NORMALIZED
th
V = V
DS
GS
I = 250
A
D
0
2
4
6
8
10
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 3.0V
GS
D
R , NORMALIZED
DS(on)
3.5
6.0
10
5.0
4.0
0
2
4
6
8
10
0
1
2
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
T = 125C
J
25C
-55C
D
V = 5V
GS
R , NORMALIZED
DS(on)
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Gate Voltage and Drain Current.
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
1
2
3
4
5
0
2
4
6
8
1 0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25
125
V = 10V
DS
GS
D
T = -55C
J
NDT410EL Rev. B1
-50
-25
0
25
50
75
100
125
150
175
0.9
0.95
1
1.05
1.1
1.15
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE (V)
I = 250A
BV , NORMALIZED
DSS
J
D
0.4
0.6
0.8
1
1.2
0.01
0.05
0.1
0.5
1
5
10
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
V = 0V
GS
T = 125C
J
25C
-55C
SD
S
0
5
1 0
1 5
20
0
2
4
6
8
1 0
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
50V
I = 2.1A
D
V = 20V
DS
80V
0.1
0.2
0.5
1
2
5
1 0
2 0
50
10
50
1 0 0
2 0 0
3 0 0
5 0 0
1 0 0 0
1 3 0 0
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0V
GS
C oss
C rss
G
D
S
V
DD
R
L
V
V
IN
OUT
V
GS
DUT
R
GEN
10%
50%
90%
10%
90%
90%
50%
V
IN
V
OUT
on
off
d(off)
f
r
d(on)
t
t
t
t
t
t
INVERTED
10%
PULSE WIDTH
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage
Variation with Current and Temperature.
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
Typical Electrical Characteristics
(continued)
NDT410EL Rev. B1
0.1
0.2
0.5
1
2
5
10
20
50
100
200
0.1
0.2
0.5
1
2
5
10
20
V , DRAIN-SOURCE VOLTAGE (V)
I
,
D
R
A
I
N
C
U
R
R
E
N
T
(
A
)
D
V = 5V
SINGLE PULSE
T = 25C
C
RDS(ON) Limit
100s
1ms
10ms
DC
10s
GS
DS
1s
10s
Figure 13. Transconductance Variation with Drain
Current and Temperature.
Figure 16. Maximum Safe
Operating Area.
Typical Electrical and Thermal Characteristics
0
2
4
6
8
10
0
2
4
6
8
1 0
1 2
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55C
J
25C
D
FS
V = 10V
DS
125C
Figure 15. Maximum Steady-State Drain Current
versus Copper Mounting Pad Area.
0
0.2
0.4
0.6
0.8
1
0.5
1
1.5
2
2.5
3
3.5
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1c
1 b
1a
4.5"x5" FR-4 Board
T = 2 5 C
Still Air
A
o
Figure 14. SOT-223 Maximum Steady- State Power
Dissipation versus Copper Mounting Pad Area.
0
0.2
0.4
0.6
0.8
1
0
0.5
1
1.5
2
2.5
3
2oz COPPER MOUNTING PAD AREA (in )
I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1 b
1a
4.5"x5" FR-4 Board
T = 2 5 C
Still Air
V = 5 V
A
o
G S
D
Figure 17. Transient Thermal Response Curve
.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
0.0001
0.001
0.01
0.1
1
1 0
1 0 0
3 0 0
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
1
2
R (t) = r(t) * R
R = See Note 1 c
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
SOT-223 Packaging
Configuration: Figure 1.0
Components
Leader Tape
500mm minimum or
62 empty pockets
Trailer Tape
300mm minimum or
38 empty pockets
SOT-223 Tape Leader and Trailer
Configuration: Figure 2.0
Cover Tape
Carrier Tape
Note/Comments
Packaging Option
SOT-223 Packaging Information
Standard
(no flow code)
D84Z
Packaging type
Reel Size
TNR
13" Dia
TNR
7" Dia
Qty per Reel/Tube/Bag
2,500
500
Box Dimension (mm)
343x64x343
184x187x47
Max qty per Box
5,000
1,000
Weight per unit (gm)
0.1246
0.1246
Weight per Reel (kg)
0.7250
0.1532
SOT-223 Unit Orientation
F852
014
F852
014
F852
014
F852
014
F63TNR Label
343mm x 342mm x 64mm
Intermediate box for Standard
184mm x 184mm x 47mm
Pizza Box for D84Z Option
F63TNR Label
LOT: CBVK741B019
FSID: PN2222A
D/C1: D9842 QTY1:
SPEC REV:
SPEC:
QTY: 3000
D/C2:
QTY2:
CPN:
N/F: F (F63TNR)3
F63TNR Label sample
F63TNR Label
Antistatic Cover Tape
Customized Label
Static Dissipative
Embossed Carrier Tape
Packaging Description:
SOT-223 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
SOT-223 Tape and Reel Data and Package Dimensions
September 1999, Rev. B
Dimensions are in millimeter
Pkg type
A0
B0
W
D0
D1
E1
E2
F
P1
P0
K0
T
Wc
Tc
SOT-223
(12mm)
6.83
+/-0.10
7.42
+/-0.10
12.0
+/-0.3
1.55
+/-0.05
1.50
+/-0.10
1.75
+/-0.10
10.25
min
5.50
+/-0.05
8.0
+/-0.1
4.0
+/-0.1
1.88
+/-0.10
0.292
+/-
0.0130
9.5
+/-0.025
0.06
+/-0.02
P1
A0
D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
12mm
7" Dia
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
5.906
150
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
12mm
13" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
7.00
178
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SOT-223 Embossed Carrier Tape
Configuration: Figure 3.0
SOT-223 Reel Configuration: Figure 4.0
SOT-223 Tape and Reel Data and Package Dimensions, continued
July 1999, Rev. B
SOT-223 (FS PKG Code 47)
SOT-223 Tape and Reel Data and Package Dimensions, continued
1 : 1
Scale 1:1 on letter size paper
Part Weight per unit (gram): 0.1246
September 1999, Rev. C
TRADEMARKS
ACExTM
CoolFETTM
CROSSVOLTTM
E
2
CMOS
TM
FACTTM
FACT Quiet SeriesTM
FAST
FASTrTM
GTOTM
HiSeCTM
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TinyLogicTM
UHCTM
VCXTM
ISOPLANARTM
MICROWIRETM
POPTM
PowerTrenchTM
QFETTM
QSTM
Quiet SeriesTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
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